CSC 456 Fall 2013/1d vb
Trends in Pipelining
Trends of Increasing Pipeline Length
With each tick of the clock, the pipeline is advanced by one stage. Having a much longer pipeline allows for each individual step to be very small and precise. Since each individual pipeline step is relatively small it is possible for the clock speed to be much faster since each step does not require as much time or work.
There is a secondary affect of longer pipelines as well. The resulting higher clock speed can also be used as a marketing point. The average user does not understand the metrics of raw processor power, but being able to compare two numbers such as 2.9Ghz vs 3.4Ghz is a simple way in which many attempt to understand different processors.
Trends of Decreasing Pipeline Length
The issue with increased pipeline length is the problem of incorrect branch predictions. The longer a pipeline is, the more stages of wasted processing have been wasted when a different branch is taken. Decreasing the pipeline length has resulted in lower clock frequencies, but equal or better IPC. A smaller pipeline suffers less of a loss for every bad prediction, and the overall performance is improved. With all processor properties, there is no simple "best" pipeline, there is always a bell curve pointing to the the most effective pipeline pipeline length for a given setup.
Latch delays can also play a role when you increase pipeline Length.. " When a performance increase is attempted by further increasing the number of stages for a processor in which the number of stages is more than 90% of the optimum for performance, the performance is found not to be increased unless the increasable latch overhead time is less than the overhead time. " - An Analysis about Increasable Latch Overhead Time for Processor Pipeline Depth Increase
An Example of Pipeline changes in Cray Systems
| Year | Name | Pipeline Length | Number of Pipelines |
|---|---|---|---|
| 1976 | Cray 1 | 3 | 12 |
| 2012 | Cray XK7 | 12 for scalar , 17 for vector | 500 cabinets * 24 blades * 4 cores * 3 pipelines per chip |
Sources
- https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&ved=0CE4QFjAA&url=http%3A%2F%2Fclasses.soe.ucsc.edu%2Fcmpe202%2FFall04%2Fpapers%2Fopteron.pdf&ei=hQsmUv6LKMnJsASb8IGACQ&usg=AFQjCNHvPcgDLJjfk0ufcd7HRA6aDAgU8w&sig2=fZvAhhwalsuZAs7GuamDHg&bvm=bv.51495398,d.cWc
- http://en.wikipedia.org/wiki/Cray-1
- http://en.wikipedia.org/wiki/XK7
- https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDkQFjAB&url=http%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fdownload%3Fdoi%3D10.1.1.93.4333%26rep%3Drep1%26type%3Dpdf&ei=BwwmUtX-D7OgsQSrxYCgDw&usg=AFQjCNFrDohjVe-SefuaJvLAJwXEFVgWYw&sig2=Hfx9Gs6MI8XtOVT3PvoDlw&bvm=bv.51495398,d.cWc
- http://www.readcube.com/articles/10.1002/ecjc.20127?locale=en