CSC/ECE 506 Spring 2013/10b ps

References

[http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html 1. http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html]
http://pic.dhe.ibm.com/infocenter/lnxinfo/v3r0m0/topic/liaaw/ordering.2006.03.13a.pdf
http://dl.acm.org/citation.cfm?id=1941553.1941594
http://home.deib.polimi.it/speziale/tech/memory_consistency/mc.html
http://homes.cs.washington.edu/~djg/papers/asf_micro2010.pdf
http://people.ee.duke.edu/~sorin/papers/asplos10_consistency.pdf
http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.06.07c.pdf
http://en.wikipedia.org/wiki/Memory_ordering
http://www.montefiore.ulg.ac.be/~pw/cours/psfiles/struct-cours12-e.pdf
http://www2.engr.arizona.edu/~ece569a/Readings/ppt/memory.ppt
http://ipdps.cc.gatech.edu/2000/fmppta/18000989.pdf
http://preshing.com/20120930/weak-vs-strong-memory-models