CSC/ECE 506 Spring 2012/ch10 sj

Limitations of cache-coherent directory-based systems

There are both hardware and software trade-offs that arise in overcoming these limitations.

High waiting time at memory operations

Sequential consistency affects performance in scalable design

Limited capacity for replication

Communicated data is automatically replicated only in the processor cache, not in local memory. This can lead to capacity misses and artifactual communication when working sets are large and include nonlocal data or when conflict misses are numerous.

High design and implementation cost

Protocols are complex and getting them right in hardware take substantial design time.

Intuition behind relaxed memory-consistency models

The System Specification

What program orders among memory operations are guaranteed to be preserved? If program order is not guaranteed to be preserved by default, what mechanisms does the system provide for a programmer to enforce order explicitly when desired?

The Programmer's Interface

The programmer's interface should provide certain rules for the programmer to follow so that (s)he doesn't have to worry about order-preserving mechanisms.

The Translation Mechanism

There needs to be a translation of the programmers' annotations to the interface exported by the system specification, so that the system may do its job.