CSC/ECE 506 Spring 2012/8a cj

MSI Protocol

Figure 1: MSI State Diagram

MESI Protocol

Figure 2: MESI State Diagram

Five State Protocols

MOESI

Figure 3: MOESI State Diagram

MESIF

Figure 4: Reduced Traffic with MESIF Protocol [1]

Protocol Performance

Figure 5: Traffic for various protocols [2]

Figure 5: Type of Miss [3]

References

1. The research of the inclusive cache used in multi-core processor
2. Parallel Computer Architecture: A Hardware/Software Approach