CSC/ECE 506 Spring 2012/8a cj
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Contents
1
MSI, MESI, MESIF, and MOESI protocols on real architectures
2
MSI Protocol
3
MESI Protocol
4
Five State Protocols
4.1
MOESI
4.2
MESIF
5
Protocol Performance
6
References
MSI, MESI, MESIF, and MOESI protocols on real architectures
MSI Protocol
Figure 1:
MSI State Diagram
MESI Protocol
Figure 2:
MESI State Diagram
Five State Protocols
MOESI
Figure 3:
MOESI State Diagram
MESIF
Figure 4:
Reduced Traffic with MESIF Protocol
[1]
Protocol Performance
Figure 5:
Type of Miss
References
The research of the inclusive cache used in multi-core processor
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