CSC/ECE 506 Fall 2007/wiki1 9 vr

Definition

Array processing is a CPU design concept which uses multiple interconnected processing elements to execute the same instruction on different data items. A control processor dispatches a single instruction stream to each of these processing elements containing a processor and a memory which execute the instruction. Communication between the processing elements is achieved by interconnecting the nodes.

Vector Processing can be described an alternative model for exploiting ILP where multiple data elements contained in vector registers are processed using pipelined vector functional units. A vector register is a linear array of vector length n-bit data elements and the pipelined units perform arithmetic operations on the data elements in parallel.

History

Flynn’s Taxonomy classifies the computers based on the number of concurrent instructions and data streams available for execution. Array and Vector Processing come under a category called SIMD i.e. single instruction multiple data, which means multiple data streams are processed for the same instruction.

During 1960’s, fear of performance stagnation pushed computer architects to look for smarter alternatives to increase the throughput. Daniel Slotnick, a Professor from Computer Science Department of University of Illinois, proposed a conceptual SIMD machine called “SOLOMON”, with 1024 1-bit processing elements each having a memory for 128 32–bit values. The machine was never built, but the design was a starting point for the advanced computer called ILLIAC-IV. It had 64 processing elements each with memory capacity of 2,048 words of 64 bit length. These elements communicated with each through an interconnect that resembled a ring. Each element was is provided a direct data path to four other elements, its immediate right and left neighbors and the neighbors spaced eight elements away. This interconnection structure is wrapped around, so that PE 63(Processing Element) is directly connected to PE 0.

The first successful implementation of vector processing architecture was CDC STAR- 100, from Central Data Corporation. It used vector registers to hold multiple data elements. It had a high startup time and very relatively slow. Vector architectures exhibited SIMD behavior by having operations that applied to all elements in a vector register.

These parallel computing architectures tried to exploit inherent data parallelism in programs.

Description

An array processor, usually has multiple processing elements each capable of performing arithmetic/logical operations and store the result in its memory. Parallelism is achieved by operating on a stream of data rather than a single element. A control processor is responsible for fetching and broadcasting the instruction which will be executed by the PEs (Processing Elements). Array processing provides more performance than a serial computing.

For example a computation that takes an array of elements and performs some operation on it would require a serial computer to process one element at a time. However an array processor does this by distributing the array elements among the PEs. Each PE may be assigned an element in an array or a set of rows. The instruction dispatched would be executed by the PE’s which communicate with each other. It is needless to say that this computing technique is suited for matrix multiplications and array operations which are extensively used in statistical analyses, numerical linear algebra, numerical solution of partial differential equations and digital signal processing calculations.

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Vector Processing as the name itself suggests uses VECTORS i.e. a series of values or elements than a SCALAR i.e. single value or an element. Vector Processors typically have

• Vector Registers

• Vector Functional units

• Scalar Units with registers and data paths,

• Vector Load Store Units

• Interconnect with is used for communication between them.

Each vector register is capable of holding multiple data elements of a definite width. A typical system would have a number of such registers. The load/store units are responsible for fetching operands and writing the results into the memory. The functional units are pipelined and they perform the arithmetic and logical operations. All of these operate on a series of values which are either residing in the main memory or in the registers. CRAY Y-MP, a supercomputer built by Cray Inc used vector processing to increase the performance.

Consider an example of multiplication of two arrays on a vector processor. The operands which are elements of the input arrays are loaded into two vector registers. The first elements of each of these vector registers are fed into a pipelined multiplication unit which performs the operation and stores the result in another vector register. All functional units are pipelined so that the overall execution time is low. The results are written back to the main memory using the load/store unit.

Importance and Trends

National Energy Research Scientific Computing Center (NERSC) at Berkeley, California has collaborations with the computer and computational science departments for several universities. This organization also ranks the most powerful supercomputers in the world based on Rmax (a benchmark from Linpack). The listings are available at www.top500.org.

Horst D Simon, the Director of NERSC Center, presented on the trends in supercomputing in December 2003. As indicated in his presentations global climate modeling and earth simulators are few of the computationally intensive examples which need supercomputers. Earth Simulator, developed for Japan Aerospace Exploration Agency is a highly parallel vector supercomputer with 640 processor nodes connected by 640x640 single-stage crossbar switches. Each node consists of 8 vector type arithmetic processor and 16 GB memory with a peak performance of 8Gflops per vector processor. It can run holistic simulations of atmosphere and oceans down to the resolution of 10 km.

Apart from the domain of supercomputers, vector processors find application in multimedia processing which is computationally intensive and places large demands on portable devices. These functions are inherently data streaming and perform same operation on multiple elements. Multiple load/store units can take advantage of the nature of inputs. The functional units are deeply pipelined to exploit ILP 9instruction level parallelism. Motorola has done a lot of research of applying these techniques for multimedia processing.

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Future

Computational simulation is one of the areas which requires supercomputing. These scientific challenges include understanding, detecting and predicting the human influence on climate and modeling the full earth system including atmosphere, ocean, land and their interactions to name a few.

Several companies like IBM, Cray Inc and SGI are doing pioneering research in supercomputing which continues to scale towards new heights.