User contributions for Shebbur
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13 April 2010
- 09:1909:19, 13 April 2010 diff hist +5 CSC/ECE 506 Spring 2010/chapter 10 →'''Sequential Consistency Model'''
- 09:0309:03, 13 April 2010 diff hist +1 CSC/ECE 506 Spring 2010/chapter 10 →'''Performance on multiprocessors'''
- 09:0309:03, 13 April 2010 diff hist +567 CSC/ECE 506 Spring 2010/chapter 10 No edit summary
- 08:5908:59, 13 April 2010 diff hist +17 CSC/ECE 506 Spring 2010/chapter 10 →'''Performance on multiprocessors'''
- 08:5808:58, 13 April 2010 diff hist +1,786 CSC/ECE 506 Spring 2010/chapter 10 →'''Performance on multiprocessors'''
- 08:3408:34, 13 April 2010 diff hist +6 CSC/ECE 506 Spring 2010/chapter 10 →'''Performance on multiprocessors'''
- 08:3308:33, 13 April 2010 diff hist +2,030 CSC/ECE 506 Spring 2010/chapter 10 →'''Performance on multiprocessors'''
- 08:1608:16, 13 April 2010 diff hist +111 CSC/ECE 506 Spring 2010/chapter 10 →'''Performance of Sequential Consistency model'''
- 07:5807:58, 13 April 2010 diff hist −8 CSC/ECE 506 Spring 2010/chapter 10 No edit summary
- 07:5707:57, 13 April 2010 diff hist +353 CSC/ECE 506 Spring 2010/chapter 10 →'''Memory Consistency models'''
- 07:5207:52, 13 April 2010 diff hist +547 CSC/ECE 506 Spring 2010/chapter 10 →'''Sequential Consistency Model'''
- 07:4707:47, 13 April 2010 diff hist +6 CSC/ECE 506 Spring 2010/chapter 10 →'''Sequential consistency'''
- 07:4507:45, 13 April 2010 diff hist +61 CSC/ECE 506 Spring 2010/chapter 10 →'''Introduction'''
- 07:4407:44, 13 April 2010 diff hist +33 CSC/ECE 506 Spring 2010/chapter 10 No edit summary
- 07:4407:44, 13 April 2010 diff hist −29 CSC/ECE 506 Spring 2010/chapter 10 →'''Memory Consistency Models - Sequential consistency'''
- 07:3607:36, 13 April 2010 diff hist +680 CSC/ECE 506 Spring 2010/chapter 10 →'''Relaxed Consistency Models'''
- 07:3407:34, 13 April 2010 diff hist +2 CSC/ECE 506 Spring 2010/chapter 10 →'''Background'''
6 April 2010
- 21:1221:12, 6 April 2010 diff hist −20 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 21:1221:12, 6 April 2010 diff hist +8 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 21:0621:06, 6 April 2010 diff hist +1 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 21:0521:05, 6 April 2010 diff hist 0 N File:Synapse1.jpg No edit summary current
- 20:5520:55, 6 April 2010 diff hist +40 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 20:5520:55, 6 April 2010 diff hist 0 N File:Synapse.jpg No edit summary current
- 20:5220:52, 6 April 2010 diff hist +180 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 05:5105:51, 6 April 2010 diff hist +1 CSC/ECE 506 Spring 2010/chapter 8 →Dragon Protocol & Xerox DragonProcessors
- 05:0905:09, 6 April 2010 diff hist −28 CSC/ECE 506 Spring 2010/chapter 8 →Special Coherence Considerations in AMD64 architectures
- 05:0805:08, 6 April 2010 diff hist +244 CSC/ECE 506 Spring 2010/chapter 8 →Special Coherence Considerations in AMD64 architectures
- 03:4203:42, 6 April 2010 diff hist +29 CSC/ECE 506 Spring 2010/chapter 8 →References
- 02:3102:31, 6 April 2010 diff hist +35 CSC/ECE 506 Spring 2010/chapter 8 →Optimization techniques on MOESI when implemented on AMD Phenom processors
- 02:3102:31, 6 April 2010 diff hist −4 CSC/ECE 506 Spring 2010/chapter 8 →Optimization techniques on MOESI when implemented on AMD Phenom(TM) processors
- 02:3002:30, 6 April 2010 diff hist −32 CSC/ECE 506 Spring 2010/chapter 8 →Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
- 02:2702:27, 6 April 2010 diff hist +1 CSC/ECE 506 Spring 2010/chapter 8 →Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
- 02:2702:27, 6 April 2010 diff hist −24 CSC/ECE 506 Spring 2010/chapter 8 →Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
- 02:2602:26, 6 April 2010 diff hist −64 CSC/ECE 506 Spring 2010/chapter 8 →Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
- 02:2302:23, 6 April 2010 diff hist −740 CSC/ECE 506 Spring 2010/chapter 8 →Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
- 02:1802:18, 6 April 2010 diff hist +290 CSC/ECE 506 Spring 2010/chapter 8 →Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
- 02:0402:04, 6 April 2010 diff hist +124 CSC/ECE 506 Spring 2010/chapter 8 →References
- 02:0402:04, 6 April 2010 diff hist 0 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 02:0402:04, 6 April 2010 diff hist +153 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 02:0002:00, 6 April 2010 diff hist +237 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 01:5701:57, 6 April 2010 diff hist +179 CSC/ECE 506 Spring 2010/chapter 8 →References
- 01:5301:53, 6 April 2010 diff hist +85 CSC/ECE 506 Spring 2010/chapter 8 →References
- 01:5201:52, 6 April 2010 diff hist +587 CSC/ECE 506 Spring 2010/chapter 8 →References
- 01:4801:48, 6 April 2010 diff hist +2 CSC/ECE 506 Spring 2010/chapter 8 →Synapse protocol and Synapse multiprocessor
- 01:4701:47, 6 April 2010 diff hist +307 CSC/ECE 506 Spring 2010/chapter 8 →MSI and Synapse multiprocessor
- 01:3001:30, 6 April 2010 diff hist +627 CSC/ECE 506 Spring 2010/chapter 8 →MSI & SGI IRIS 4D Processors
- 00:5500:55, 6 April 2010 diff hist +131 CSC/ECE 506 Spring 2010/chapter 8 →MSI & SGI IRIS 4D Processors
- 00:5400:54, 6 April 2010 diff hist 0 N File:MSI.jpg No edit summary
- 00:4700:47, 6 April 2010 diff hist +18 CSC/ECE 506 Spring 2010/chapter 8 →Introduction to Bus-based cache coherence in real machines
- 00:2100:21, 6 April 2010 diff hist +24 CSC/ECE 506 Spring 2010/chapter 8 →SGI
