User contributions for Shebbur

6 April 2010

• 00:2000:20, 6 April 2010 diff hist +78‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MSI & SGI IRIS 4D Processors
• 00:1600:16, 6 April 2010 diff hist +1,037‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MSI & SGI IRIS 4D Processors
• 00:0700:07, 6 April 2010 diff hist +4‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MSI & SGI IRIS 4D series
• 00:0700:07, 6 April 2010 diff hist +303‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MSI & SGI IRIS 4D series
• 00:0200:02, 6 April 2010 diff hist +44‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MSI & SGI IRIS 4D series
• 00:0200:02, 6 April 2010 diff hist +1,552‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MSI & SGI IRIS 4D series

5 April 2010

• 23:2123:21, 5 April 2010 diff hist +27‎ CSC/ECE 506 Spring 2010/chapter 8 ‎No edit summary
• 21:3621:36, 5 April 2010 diff hist +11‎ CSC/ECE 506 Spring 2010/chapter 8 ‎No edit summary
• 21:3521:35, 5 April 2010 diff hist −14‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎'''Intel'''
• 21:3521:35, 5 April 2010 diff hist −2‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎'''Intel'''

27 March 2010

• 01:5001:50, 27 March 2010 diff hist 0‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎AMD Opteron memory Architecture
• 01:4701:47, 27 March 2010 diff hist +103‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 01:4301:43, 27 March 2010 diff hist 0‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:3201:32, 27 March 2010 diff hist −6‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
• 01:3201:32, 27 March 2010 diff hist +134‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
• 01:3001:30, 27 March 2010 diff hist +90‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎CMP Implementation in Intel Architecture
• 01:2801:28, 27 March 2010 diff hist +228‎ CSC/ECE 506 Spring 2010/chapter 8 ‎No edit summary
• 01:2701:27, 27 March 2010 diff hist +252‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MESI & Intel Processors
• 01:2501:25, 27 March 2010 diff hist +36‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎CMP Implementation in Intel Architecture
• 01:2401:24, 27 March 2010 diff hist +90‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:2301:23, 27 March 2010 diff hist +30‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:2201:22, 27 March 2010 diff hist +129‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:2101:21, 27 March 2010 diff hist +259‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:2001:20, 27 March 2010 diff hist +33‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:1901:19, 27 March 2010 diff hist +35‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:1801:18, 27 March 2010 diff hist +36‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
• 01:1701:17, 27 March 2010 diff hist +366‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 01:1201:12, 27 March 2010 diff hist +102‎ CSC/ECE 506 Spring 2010/chapter 8 ‎No edit summary
• 01:1201:12, 27 March 2010 diff hist +65‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 01:1001:10, 27 March 2010 diff hist −4‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:1001:10, 27 March 2010 diff hist +174‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎AMD Opteron memory Architecture
• 01:0301:03, 27 March 2010 diff hist −1‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 01:0301:03, 27 March 2010 diff hist 0‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 01:0201:02, 27 March 2010 diff hist +128‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 01:0201:02, 27 March 2010 diff hist +230‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎MOESI & AMD Processors
• 00:5900:59, 27 March 2010 diff hist +137‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 00:5800:58, 27 March 2010 diff hist +212‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
• 00:5000:50, 27 March 2010 diff hist 0‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 00:5000:50, 27 March 2010 diff hist −7‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 00:4900:49, 27 March 2010 diff hist +132‎ CSC/ECE 506 Spring 2010/chapter 8 ‎No edit summary
• 00:4800:48, 27 March 2010 diff hist −2‎ CSC/ECE 506 Spring 2010/chapter 8 ‎No edit summary
• 00:4800:48, 27 March 2010 diff hist −4‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 00:4700:47, 27 March 2010 diff hist +2‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎References
• 00:4700:47, 27 March 2010 diff hist +19‎ CSC/ECE 506 Spring 2010/chapter 8 ‎No edit summary
• 00:0600:06, 27 March 2010 diff hist −9‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Special Coherency Considerations in AMD64 architectures
• 00:0500:05, 27 March 2010 diff hist +4‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Special Coherency Considerations in AMD64 architectures

26 March 2010

• 23:2623:26, 26 March 2010 diff hist +173‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Special Coherency Considerations in AMD64 architectures
• 23:1723:17, 26 March 2010 diff hist +6‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Optimizing Inter-Core Data Transfer on AMD Phenom(TM) processors by using some optimization technique on MOESI
• 23:1723:17, 26 March 2010 diff hist +6‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎Special Coherency Considerations in AMD64 architectures
• 23:1623:16, 26 March 2010 diff hist +6‎ CSC/ECE 506 Spring 2010/chapter 8 ‎ →‎AMD Opteron memory Architecture