CSC/ECE 506 Spring 2012/preface
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Contents
1
Preface
1.1
Chapter 1a:
Supercomputer comparisons
1.2
Chapter 1b:
Does Moore's Law still hold?
1.3
Chapter 1c:
MISD architectures
1.4
Chapter 2a:
SAS programming on distributed-memory machines
1.5
Chapter 2b:
Data parallelism in GPUs
1.6
Chapter 3a:
Patterns of parallel programming
1.7
Chapter 3b:
Map Reduce
1.8
Chapter 4a:
Automatic parallelism and its limitations
1.9
Chapter 4b:
The limits to speedup
1.10
Chapter 5a:
Other linked data structures
1.11
Chapter 6b:
Multiprocessor issues with write buffers
1.12
Chapter 7b:
TLB coherence
1.13
Chapter 8a:
MSI, MESI, MESIF, and MOESI protocols on real architectures
1.14
Chapter 8b:
8b. Update and adaptive coherence protocols on real architectures, and power considerations
1.15
Chapter 9a:
Reducing locking overhead
1.16
Chapter 10a:
Prefetching and consistency models
1.17
Chapter 10b:
Use of consistency models in current multiprocessors
1.18
Chapter 11a:
Performance of DSM systems
1.19
Chapter 11b:
Improvements to directory-based cache-coherence animations
1.20
Chapter 12a:
New interconnection topologies
1.21
Chapter 12b:
On-chip interconnects
Preface
Chapter 1a:
Supercomputer comparisons
Chapter 1b:
Does Moore's Law still hold?
Chapter 1c:
MISD architectures
Chapter 2a:
SAS programming on distributed-memory machines
Chapter 2b:
Data parallelism in GPUs
Chapter 3a:
Patterns of parallel programming
Chapter 3b:
Map Reduce
Chapter 4a:
Automatic parallelism and its limitations
Chapter 4b:
The limits to speedup
Chapter 5a:
Other linked data structures
Chapter 6b:
Multiprocessor issues with write buffers
Chapter 7b:
TLB coherence
Chapter 8a:
MSI, MESI, MESIF, and MOESI protocols on real architectures
Chapter 8b:
8b. Update and adaptive coherence protocols on real architectures, and power considerations
Chapter 9a:
Reducing locking overhead
Chapter 10a:
Prefetching and consistency models
Chapter 10b:
Use of consistency models in current multiprocessors
Chapter 11a:
Performance of DSM systems
Chapter 11b:
Improvements to directory-based cache-coherence animations
Chapter 12a:
New interconnection topologies
Chapter 12b:
On-chip interconnects
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