CSC/ECE 506 Fall 2007/wiki2 5 as
Cache sizes in multicore architectures
Topic - Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.
Multicore Processors | |||||
---|---|---|---|---|---|
Processor Name | Number of Levels | Line Size | Cache Size | Associativity | Coherence Protocol |
AMD Athlon 64 X2 | 2 | 64 bytes (for both L1 & L2) | L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core |
L1 - 2 way (Data and Instruction cache) L2 - 16 way associative |
Modified Owner Exclusive Shared Invalid (MOESI) |
AMD Athlon 64 FX | 2 | 64 bytes (for both L1 & L2) | L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core |
L1 - 2 way (Data and Instruction cache) L2 - 16 way associative |
Modified Owner Exclusive Shared Invalid (MOESI) |
AMD Athlon Opteron (marketed for servers) |
2 | 64 bytes (for both L1 & L2) | L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core |
L1 - 2 way (Data and Instruction cache) L2 - 16 way associative |
Modified Owner Exclusive Shared Invalid (MOESI) |
Intel Pentium D | 2 | L1 - 64 byte lines L2 - 128 byte lines |
L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core |
L1 - 4 way L2 - 8 way |
Modified Exclusive Shared Invalid (MESI) |
Intel Pentium Dual Core | 2 | L1 - 64 byte lines L2 - 64 byte lines |
L1 - 32 KB (both Data and Instruction cache) L2 - 1MB or 2MB per core |
L1 - 4 way L2 - 8 way |
Modified Exclusive Shared Invalid (MESI) |
Intel Core 2 Duo | 2 | L1 - 64 byte lines L2 - 64 byte lines |
L1 - 32 KB (each for Data and Instruction cache) L2 - 2MB or 4MB |
L1 - 4 way L2 - 8 way |
Modified Exclusive Shared Invalid (MESI) |
Broadcom SiByte SB1250 | 2 | L1 - 32 byte lines L2 - 32 byte lines |
L1 - 32 KB (a piece for Data and Instruction caches) L2 - 512KB |
L1 - 2 way L2 - 4 way |
Modified Exclusive Shared Invalid (MESI) |
Sun Microsystems UltraSPARC IV | 2 | L1 - 128byte lines L2 - 128 byte lines |
L1 - 64KB data, 32KB instruction L2 - up to 16MB |
L2 - 2 way | Modified Owner Exclusive Shared Invalid (MOESI) |
IBM Cell Processor | 2 | Not Available | L1 - 32 KB (a piece for both data and instruction caches) L2 - 512KB |
L1 - 2 way instruction, 4 way data L2 - 8 way |
Modified Exclusive Shared Invalid (MESI) |
Singlecore Processors | |||||
AMD Athlon 64 | 2 | L1 - 64 byte lines L2 - 64 byte lines |
L1 - 64 KB (each for Data and Instruction cache) L2 - 512KB |
L1 - 2 way L2 - 16 way |
Modified Owner Exclusive Shared Invalid (MOESI) |
Intel Pentium 4 | 2 | L1 - 64 byte lines L2 - 128 byte lines |
L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)) L2 -256KB, 512KB or 1MB |
L1 - 4 way L2 - 8 way |
Modified Exclusive Shared Invalid (MESI) |
Intel PentiumIII 600 | 2 | L1 - 32 byte lines L2 - 32 byte lines |
L1 - 16 KB data, 16KB Instruction L2 - 256KB |
L1 - 4 way L2 - 8 way |
Modified Exclusive Shared Invalid (MESI) |
AMD K6 / K6 III | 2 | L1 - 32 byte lines L2 - 32 byte lines |
L1 - 32KB data, 32KB instruction L2 - 256KB |
L1 - 2 way L2 - 4 way |
Modified Exclusive Shared Invalid (MESI) |
Conclusion
From the above table we find that there isn't much difference in the specifications of caches used in multi-core and single-core processors.
References
[1] http://www.amd.com/us-en/Processors/ProductInformation
[2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250
[3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor
[4] http://www.intel.com/products/processor
[5] http://www.sun.com/processors/UltraSPARC-IV/
[6] http://www.sun.com/processors/UltraSPARC-IV+/
[7] http://www.sun.com/processors/UltraSPARC-T1/specs.xml
[8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html
[9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html
[10] http://www.netlib.org/utk/papers/advanced-computers/power4.html
[11] http://www.netlib.org/utk/papers/advanced-computers/power5.html
[12] http://en.wikipedia.org/wiki/Cell_microprocessor