CSC/ECE 506 Spring 2012/7b pk

TLB (Translation Lookaside Buffer) Coherence in Multiprocessing

Background - Virtual Memory, Paging and TLB

In this section we explain the terminology of the set-up where TLBs are used.

A process running on a CPU has its own view of memory - "Virtual Memory" as opposed to actual physical memory. Virtual memory management scheme allows programs to exceed the size of physical memory space. Virtual memory operates by executing programs only partially resident in memory while relying on hardware and the operating system to bring the missing items into main memory when needed.

Paging is a memory-management scheme that permits the physical address space of a process to be non-contiguous. The basic method involves breaking physical memory into fixed-size blocks called frames and breaking the virtual memory into blocks of the same size called pages. When a process is to be executed its pages are loaded into any available memory frames from the backing storage (for example-a hard drive).

Each process has a page table (software construct managed by operating system that is kept in main memory) that maintains a mapping of virtual pages to physical pages. For a process, a pointer to the page table (Page-Table base register) is stored in a register. Changing page table requires changing only this one register, substantially reducing the context-switch time.

The hardware support for paging is shown in figure. Every address is divided into two parts – a page number (p) and a page offset (d). The page number is used as an index into the page table. The page table contains the base address of each page in physical memory. The base address is combined with the page offset to define the physical memory address that is sent to the memory unit.