CSC/ECE 506 Fall 2007/wiki 2 5 2281

Objective

Cache sizes in multicore architectures Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

Multi-core Architecture	Number of levels	Line Size	Cache Size	Associativity	Latency	Is the Level shared	Coherence Protocol used
AMD Opteron Processor	2	-	64 Byte L1 Cache - Data and Instruction Cache Separated, 1024 KByte L2	2 Way Associative ECC Protected L1 Data Cache & Parity Protected Instruction Cache; 16 Way Associative Parity Protected L2 Cache	Two 64 bit operations per 3 cycle latency	No	Exclusive cache architecture
AMD Athlon X2 Dual Core	2	-	64 Byte L1 Cache - Data and Instruction Cache Separated, 1024 KByte L2	2 Way Associative ECC Protected L1 Data Cache & Parity Protected Instruction Cache; 16 Way Associative Parity Protected L2 Cache	Two 64 bit operations per 3 cycle latency	No	Exclusive cache architecture