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| name = Sidebar | outertitle = Useful Definitions | topimage = | pretitle = | title = | image = | heading1 = PMT(Page Mapping Table) | content1 = This is an in-memory data structure that primarily helps the operating system map two address spaces two one another: virtual memory and physical memory. In addition to this mapping information, the PMT also stores additional data fields to keep track of whether the virtual memory has been loaded in physical memory, permissions and utilization metrics. Coupled with the TLB, the PMT is a critical component of virtual memory systems. Learn more about page tables here.

| heading2 =PTE (Page Table Entry) | content2 = A row in a page mapping table that relates a single page in virtual memory to a physical memory address or a page frame.

| heading3 =TLB(Translation Look-Aside Buffer) | content3 = Associative, high-speed memory used to cache page table information and speed up virtual memory references from the processor.

| heading4 =Presence Bit | content4 = One of the data elements in each PMT entry. Indicates whether the page is loaded in main memory (versus stored to disk).

| heading5 =Safe Change | content5 = A type of update that can be made to a PMT safely without also updating the cached TLB counterpart.

| heading6 =TLB Coherence Strategy | content6 = A process or system for maintaining the consistency of information between the processor TLBs and the PMT entries.

| heading7 =IDT (Interrupt Descriptor Table) | content7 = A vector-based data structure used to communicate information between processors during an inter-processor interrupt.

| heading8 =Interrupt | content8 = A hardware or software based method for signalling to a processor that there is work for it.

| heading9 =ASID (Address Space Identifier) | content9 = A number assigned to process that is unique within the scope of a processor for a specified time period. A process may be assigned multiple ASIDs across time. Used with the TLB entries, the ASID helps the discard stale TLB entries.

| heading10 =Hierarchical TLBs | content10 = Is analogus concept for TLBS as multilevel L1 and L2 cache

| heading11 =Page Table Base Register | content11 = Pointer to page table location is maintained in this register

| heading12 =UNITD protocol | content12 = A protocol that combine cache and TLB coherence proposed by Romanescu/Lebeck/Sorin/Bracy

| heading13 =Validation based approach | content13 = In this approach TLB entries are not updated until used

| heading14 =Virtual Index Cache | content14 = Cache that stores data based on virtual page number

| heading15 =TLB Shootdown | content15 = Software based TLB coherence method that requires one processor to shoot-down/disable TLB entries in other processors before providing them with a new TLB entry