CSC/ECE 506 Spring 2012/preface: Difference between revisions
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(/* Chapter 11: Distributed Shared Memory Multiprocessors Spring_2012/11a_hn[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_ht Spring_2012/11a_ht[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_sc Spr) |
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== Chapter 10b: '' Use of consistency models in current multiprocessors'' == | == Chapter 10b: '' Use of consistency models in current multiprocessors'' == | ||
=Chapter 11: Distributed Shared Memory Multiprocessors <ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_hn Spring_2012/11a_hn]</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_ht Spring_2012/11a_ht</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_sc Spring_2012/11a_sc</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch11_BB_EP Spring_2011/ch11_BB_EP</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch11_DJ Spring_2011/ch11_DJ</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch11_sw Spring_2011/ch11_sw</ref>= | =Chapter 11: Distributed Shared Memory Multiprocessors <ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_hn Spring_2012/11a_hn]</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_ht Spring_2012/11a_ht]</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/11a_sc Spring_2012/11a_sc]</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch11_BB_EP Spring_2011/ch11_BB_EP]</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch11_DJ Spring_2011/ch11_DJ]</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2011/ch11_sw Spring_2011/ch11_sw]</ref>= | ||
== Chapter 11a: ''Performance of DSM systems'' == | == Chapter 11a: ''Performance of DSM systems'' == | ||
== Chapter 11b: ''Improvements to directory-based cache-coherence animations'' == | == Chapter 11b: ''Improvements to directory-based cache-coherence animations'' == | ||
Revision as of 18:07, 15 April 2012
Preface
Chapter 1: Perspectives <ref>Spring_2012/1a_hv</ref><ref>Spring_2012/1a_mw</ref> <ref>Spring_2012/1a_ry</ref> <ref>Spring_2012/1b_ap</ref> <ref>Spring_2012/1b_as </ref> <ref> Spring_2012/1b_ps</ref> <ref>Spring_2012/1c_12</ref> <ref> Spring_2012/1c_cl </ref> <ref>Spring_2011/ch1_LL </ref> <ref>Spring_2012/1c_dm </ref>
Chapter 1: Supercomputer comparisons
Chapter 1b: Does Moore's Law still hold?
Chapter 1c: MISD architectures
Chapter 2: Parallel Programming Models <ref>Spring_2012/2a_bm </ref> <ref> Spring_2012/2a_va </ref><ref> Spring_2012/ch2b_cm </ref><ref>Spring_2011/ch2_cl </ref><ref> Spring_2011/ch2_dm</ref><ref>Spring_2011/ch2_JR </ref><ref> Spring_2011/ch2a_mc </ref>
Chapter 2a: SAS programming on distributed-memory machines
Chapter 2b: Data parallelism in GPUs
Chapter 3a: Patterns of parallel programming
Chapter 3b: Map Reduce
Chapter 4a: Automatic parallelism and its limitations
Chapter 4b: The limits to speedup
Chapter 5:Parallel Programming for Linked Data Structures <ref>Spring_2012/ch5a_ja</ref><ref>Spring_2011/ch5_LL</ref>
Chapter 5a: Other linked data structures
Chapter 6: Introduction to Memory Hierarchy Organization <ref>Spring_2011/6a_ms</ref><ref>Spring_2012/6b_am</ref><ref>Spring_2012/6b_pa</ref><ref>Spring_2011/ch6a_ep</ref><ref>Spring_2011/ch6a_jp</ref><ref>Spring_2011/ch6b_ab</ref><ref>Spring_2011/ch6b_df</ref>
Chapter 6b: Multiprocessor issues with write buffers
Chapter 7b: TLB coherence
Chapter 8: Bus-Based Coherent Multiprocessors <ref>Spring_2011/ch8_cl</ref><ref>Spring_2011/ch8_mc</ref> <ref>Spring_2012/8a_cj</ref> <ref>Spring_2012/8a_cm</ref> <ref>Spring_2012/8a_fu</ref> <ref>Spring_2012/8b_va</ref>
Chapter 8a: MSI, MESI, MESIF, and MOESI protocols on real architectures
Chapter 8b: 8b. Update and adaptive coherence protocols on real architectures, and power considerations
Chapter 9: Hardware Support for Synchronization <ref>Spring_2011/ch9_ms</ref><ref>Spring_2012/9a_mm</ref><ref>Spring_2012/9a_mm</ref><ref>Spring_2012/9a_mm</ref>
Chapter 9a: Reducing locking overhead
Chapter 10: Memory Consistency Models<ref>Spring_2012/10a_dr</ref><ref>Spring_2012/10a_jp</ref><ref>Spring_2012/10a_vm</ref><ref>Spring_2012/10b_sr</ref><ref>Spring_2012/ch10_sj</ref><ref>Spring_2011/ch10_MC</ref><ref>Spring_2011/ch10_sb</ref><ref>Spring_2011/ch10_sj</ref><ref>Spring_2011/ch10a_dc</ref>
Chapter 10a: Prefetching and consistency models
Chapter 10b: Use of consistency models in current multiprocessors
Chapter 11a: Performance of DSM systems
Chapter 11b: Improvements to directory-based cache-coherence animations
Chapter 12: Interconnection Network Architecture
Chapter 12a: New interconnection topologies
Chapter 12b: On-chip interconnects
References
<references/>