CSC/ECE 506 Spring 2012/preface: Difference between revisions
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= Preface = | = Preface = | ||
= Chapter 1: Perspectives <ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_hv]</ref> | = Chapter 1: Perspectives <ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_hv]</ref><ref>[http://expertiza.csc.ncsu.edu/wiki/index.php/CSC/ECE_506_Spring_2012/1a_mw],<ref> = | ||
== Chapter 1: ''Supercomputer comparisons'' == | == Chapter 1: ''Supercomputer comparisons'' == | ||
== Chapter 1b: ''Does Moore's Law still hold?'' == | == Chapter 1b: ''Does Moore's Law still hold?'' == | ||
== Chapter 1c: ''MISD architectures'' == | == Chapter 1c: ''MISD architectures'' == | ||
= Chapter 2: Parallel Programming Models= | = Chapter 2: Parallel Programming Models= | ||
== Chapter 2a: ''SAS programming on distributed-memory machines'' == | == Chapter 2a: ''SAS programming on distributed-memory machines'' == | ||
Revision as of 16:56, 15 April 2012
Preface
Chapter 1: Perspectives <ref>[1]</ref><ref>[2],<ref>
Chapter 1: Supercomputer comparisons
Chapter 1b: Does Moore's Law still hold?
Chapter 1c: MISD architectures
Chapter 2: Parallel Programming Models
Chapter 2a: SAS programming on distributed-memory machines
Chapter 2b: Data parallelism in GPUs
Chapter 3a: Patterns of parallel programming
Chapter 3b: Map Reduce
Chapter 4a: Automatic parallelism and its limitations
Chapter 4b: The limits to speedup
Chapter 5:Parallel Programming for Linked Data Structures
Chapter 5a: Other linked data structures
Chapter 6: Introduction to Memory Hierarchy Organization
Chapter 6b: Multiprocessor issues with write buffers
=Chapter 7:Introduction to Shared Memory Multiprocessors+
Chapter 7b: TLB coherence
=Chapter 8: Bus-Based Coherent Multiprocessors
Chapter 8a: MSI, MESI, MESIF, and MOESI protocols on real architectures
Chapter 8b: 8b. Update and adaptive coherence protocols on real architectures, and power considerations
Chapter 9: Hardware Support for Synchronization
Chapter 9a: Reducing locking overhead
Chapter 10: Memory Consistency Models
Chapter 10a: Prefetching and consistency models
Chapter 10b: Use of consistency models in current multiprocessors
Chapter 11a: Performance of DSM systems
Chapter 11b: Improvements to directory-based cache-coherence animations
Chapter 12: Interconnection Network Architecture
Chapter 12a: New interconnection topologies
Chapter 12b: On-chip interconnects
References
<references/>