CSC/ECE 506 Spring 2012/preface: Difference between revisions

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== Chapter 11b:  ''Improvements to directory-based cache-coherence animations'' ==
== Chapter 11b:  ''Improvements to directory-based cache-coherence animations'' ==
== Chapter 12a:  ''New interconnection topologies'' ==
== Chapter 12a:  ''New interconnection topologies'' ==
== Chapter 12b: ''On-chip interconnects''
== Chapter 12b: ''On-chip interconnects'' ==

Revision as of 14:44, 15 April 2012

Preface

Chapter 1a: Supercomputer comparisons

Chapter 1b: Does Moore's Law still hold?

Chapter 1c: MISD architectures

Chapter 2a: SAS programming on distributed-memory machines

Chapter 2b: Data parallelism in GPUs

Chapter 3a: Patterns of parallel programming

Chapter 3b: Map Reduce

Chapter 4a: Automatic parallelism and its limitations

Chapter 4b: The limits to speedup

Chapter 5a: Other linked data structures

Chapter 6b: Multiprocessor issues with write buffers

Chapter 7b: TLB coherence

Chapter 8a: MSI, MESI, MESIF, and MOESI protocols on real architectures

Chapter 8b: 8b. Update and adaptive coherence protocols on real architectures, and power considerations

Chapter 9a: Reducing locking overhead

Chapter 10a: Prefetching and consistency models

Chapter 10b: Use of consistency models in current multiprocessors

Chapter 11a: Performance of DSM systems

Chapter 11b: Improvements to directory-based cache-coherence animations

Chapter 12a: New interconnection topologies

Chapter 12b: On-chip interconnects

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