CSC/ECE 506 Spring 2012/10b sr: Difference between revisions
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'''Use of consistency models in current multiprocessors''' | '''Use of consistency models in current multiprocessors''' | ||
The memory consistency model of a shared memory system determines the order in which memory operations will appear to execute to the programmer. This article describes how consistency is used in multiprocessors today and later digs into the details of popular consistency models in use today. The impact of these models on the multiprocessor performance is also discussed. The article finishes off with a discussion about how the consistency models perform with larger multiprocessors. | |||
== Introduction == | == Introduction == | ||
Revision as of 05:22, 4 April 2012
Use of consistency models in current multiprocessors
The memory consistency model of a shared memory system determines the order in which memory operations will appear to execute to the programmer. This article describes how consistency is used in multiprocessors today and later digs into the details of popular consistency models in use today. The impact of these models on the multiprocessor performance is also discussed. The article finishes off with a discussion about how the consistency models perform with larger multiprocessors.
Introduction
Consistency in current-day multiprocessors
Consistency models used
- address translation aware memory consistency
- causal consistency
- delta consistency
- entry consistency
- eventual consistency
- fork consistency
- linearizability (also known as strict or atomic consistency)
- one-copy serializability
- PRAM consistency (also known as FIFO consistency)
- release consistency
- sequential consistency
- serializability
- vector-field consistency
- weak consistency
- strong consistency