CSC/ECE 506 Spring 2012/10a dr: Difference between revisions
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==Consistency models== | ==Consistency models== | ||
The memory consistency model in shared memory parallel programming controls the order in which memory operations performed by one thread may be observed by another. The most natural model for programmers is to have memory accesses appear to take effect in the order specified in the original program. Language designers have been reluctant to use this strong semantics, called sequential consistency, due to concerns over the performance of memory fence instructions and related mechanisms that guarantee order. | |||
===F === | ===F === | ||
Revision as of 22:38, 2 April 2012
Prefetching and consistency models
Introduction
In
Prefetching
a
B
h
C
If k
D
controversial.
Consistency models
The memory consistency model in shared memory parallel programming controls the order in which memory operations performed by one thread may be observed by another. The most natural model for programmers is to have memory accesses appear to take effect in the order specified in the original program. Language designers have been reluctant to use this strong semantics, called sequential consistency, due to concerns over the performance of memory fence instructions and related mechanisms that guarantee order.
F
When
G
So
Conclusion
H
Using
I
Even
External links
1. Sequential hardware prefetching in shared-memory multiprocessors
References
<references/>