User:Stchen: Difference between revisions
Jump to navigation
Jump to search
| Line 3: | Line 3: | ||
In parallel computer architectures, '''cache coherence''' refers to the consistency of data that is stored throughout the [http://en.wikipedia.org/wiki/Cache_(computing) caches] on individual processors or throughout the shared memory. The problem here is that | In parallel computer architectures, '''cache coherence''' refers to the consistency of data that is stored throughout the [http://en.wikipedia.org/wiki/Cache_(computing) caches] on individual processors or throughout the shared memory. The problem here is that | ||
[[Image:Cache Coherency Generic.png|thumb| Multiple Caches of Shared Resource]] | <center>[[Image:Cache Coherency Generic.png|thumb|400px| Multiple Caches of Shared Resource]]</center> | ||
<center> '''Figure 1. Multiple Caches of Shared Resource''' </center> | <center> '''Figure 1. Multiple Caches of Shared Resource''' </center> | ||
Revision as of 02:48, 21 March 2012
Introduction to Update and Adaptive Coherence Protocols on Real Architectures
In parallel computer architectures, cache coherence refers to the consistency of data that is stored throughout the caches on individual processors or throughout the shared memory. The problem here is that
Update and Adaptive Coherence Protocols are used to solve the cache coherency problem.
According to Solihin textbook, page number 229, "One of the drawbacks of an invalidate-based protocol is that it incurs high number of coherence misses." What this means is that when a read has been made to an invalidated block, there will be a cache miss and serving this miss can create a high latency. To solve this, one can use a update coherence protocol, or an adaptive coherence protocol.
Update Coherence Protocol
BOOM