CSC/ECE 506 Spring 2012/8a cj: Difference between revisions
Jump to navigation
Jump to search
No edit summary |
|||
| Line 11: | Line 11: | ||
[[Image:MESIFVMESI.jpg|thumb|upright|center|450px|<b>Figure 4:</b> Reduced Traffic with MESIF Protocol [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1]]] | [[Image:MESIFVMESI.jpg|thumb|upright|center|450px|<b>Figure 4:</b> Reduced Traffic with MESIF Protocol [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1]]] | ||
=Protocol Performance= | =Protocol Performance= | ||
[[Image:TypeOfMiss.jpg|thumb|upright|center|450px|<b>Figure 5:</b> Type of Miss]] | |||
=References= | =References= | ||
# [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1 The research of the inclusive cache used in multi-core processor] | # [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1 The research of the inclusive cache used in multi-core processor] | ||
Revision as of 14:08, 20 March 2012
MSI, MESI, MESIF, and MOESI protocols on real architectures
MSI Protocol
MESI Protocol
Five State Protocols
MOESI
MESIF
Protocol Performance
