CSC/ECE 506 Fall 2007/wiki3 8 a1

Topic Background

The protocols discussed here were created to allow cache coherence to be maintained on a system that has no global bus system that allows snooping to take place, and, has distributed memory that is physically separated. These systems usually consist of PCM (Processor-Control-Memory) nodes connected by a network; the systems also have network assists to allow communication to take place.

For a system to be coherent it must:

1. Provide a state machine for the protocol
2. Manage the coherence protocol
   • Determine when the coherence protocol should be used
   • Find information on the current cache block in other caches
   • Find out where other copies of the current cache block are located
   • Communicate with the other copies

The protocols discussed here are managed by the scalable system by using a directory-based approach. Information on all cache blocks is kept in a directory that is associated with each block of memory. When a cache miss arises the directory information is checked and all other caches containing a copy of the desired block are contacted. The information contained in the directories consists of a dirty bit, and some state information that will allow action to be taken when there is a cache miss and the directory information needs to be referenced.

Links

IEEE SCI Standard Abstract and Content Summary - http://standards.ieee.org/reading/ieee/std_public/description/busarch/1596-1992_desc.html
IEEE SCI on ieexplore - http://ieeexplore.ieee.org/iel5/285/3365/00113656.pdf?tp=&arnumber=113656&isnumber=3365
4BA2 Technology Survery on SCI (good overview) - http://ntrg.cs.tcd.ie/undergrad/4ba2.05/group12/index.html

References

CSC/ECE 506 Lecture Notes, Fall 2007