CSC/ECE 506 Spring 2012/1c 12: Difference between revisions

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It is widely believed that no actual MISD computer exists in practice.   
It is widely believed that no actual MISD computer exists in practice.   


Some arguments exist that pipelined vector processors could be considered example of MISD architecture due to the fact that a different operation is performed on the data stream as it flows from stage to stage.[[#References|<sup>[6]</sup>]]  The argument against this idea is that individual processing elements in each stage do not technically fetch their operations from an instruction cache[[#References|<sup>[6]</sup>]], but are more similar to a function specific, or [http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC], chip.   
Some arguments exist that pipelined vector processors could be considered example of MISD architecture due to the fact that a different operation is performed on the data stream as it flows from stage to stage.[[#References|<sup>[6]</sup>]]  The argument against this idea is that individual processing elements in each stage do not technically fetch their operations from an instruction cache[[#References|<sup>[6]</sup>]], but are more similar to a function specific, or [http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC], chip.  Other arguments exist that MISD VLSI architectures that use a "recursive divide and conquer approach to pattern matching"[[#References|<sup>[8]</sup>]] is ideal for applications which require multiple pattern matching in large data streams that lack any preprocessed indexes for lookups[[#References|<sup>[8]</sup>]].


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Revision as of 22:35, 26 January 2012

MISD

Micheal J. Flynn introduced the idea of an MISD (Multiple Instruction, Single Data) computer architectures in his original taxonomy in 1966.[1]

Dr. Yan Solihin defines MISD as "..an architecture in which multiple processing elements execute from different instruction streams, and data is passed from one processing element to the next."[2] He also notes that MISD architectures are restricted to certain types of computations due to the requirement of data-passing between processing elements.[2] Each processing element executes different instructions on the data stream.[3] Every time the data is processed by a processing element, we can always argu that the data is no longer the original data introduced at the start of the stream.[4]

MISD computer architecture outline.
From NCSU CSC/ECE 506 Spring 2012 Lecture 1 notes[5].

From the image, we see that the data stream has one clear entrance and exit into the system. Each processing element has access to a collective and/or individual instruction cache. Depending on the specific system described, each processing element is generally function specific or predestined; but in some systems (similar to iWarp), each processing element may be quite advanced.

MISD Computers

It is widely believed that no actual MISD computer exists in practice.

Some arguments exist that pipelined vector processors could be considered example of MISD architecture due to the fact that a different operation is performed on the data stream as it flows from stage to stage.[6] The argument against this idea is that individual processing elements in each stage do not technically fetch their operations from an instruction cache[6], but are more similar to a function specific, or ASIC, chip. Other arguments exist that MISD VLSI architectures that use a "recursive divide and conquer approach to pattern matching"[8] is ideal for applications which require multiple pattern matching in large data streams that lack any preprocessed indexes for lookups[8].



Systolic array

"Systolic array is an arrangement of processors in an array(often rectangular)where data flows synchronously across the array between neighbors"[7]

References

  1. Flynn, M. (1972). "Some Computer Organizations and Their Effectiveness". IEEE Trans. Comput. C-21: 948.
  2. Solihin, Y. (2008). "Fundamentals of Parallel Computer Architecture: Multichip and Multicore Systems". Solihin Publishing & Consulting LLC. C-1: 12.
  3. CSC 8383 Lecuture 5
  4. MISD wiki
  5. ECE506 Spring 2012 Lecture 1
  6. 3.1.3 MISD Computers
  7. Laiq hasan,Yahya M.Khawaja,Abdul Bais,"A Systolic Array Architecture for the Smith-Waterman Algorithm with High Performance Cell Design" in IADIS European Conference Data Mining, 2008, pp: 37
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