CSC/ECE 506 Spring 2011/ch11 sw: Difference between revisions
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This article discusses the design of scalable shared memory [http://en.wikipedia.org/wiki/Multiprocessing multiprocessors]. As we know, bus-based multiprocessor possess the disadvantage of being non-scalable. So, a new system called [http://en.wikipedia.org/wiki/Distributed_shared_memory Distributed Shared Memory] was introduced wherein, accessing different parts of memory takes different times. Thus, a DSM is more scalable than a bus-based multiprocessors. But as the size of the DSM increases, so does the cost for the hardware support needed for it. | This article discusses the design of scalable shared memory [http://en.wikipedia.org/wiki/Multiprocessing multiprocessors]. As we know, bus-based multiprocessor possess the disadvantage of being non-scalable. So, a new system called [http://en.wikipedia.org/wiki/Distributed_shared_memory Distributed Shared Memory] was introduced wherein, accessing different parts of memory takes different times. Thus, a DSM is more scalable than a bus-based multiprocessors. But as the size of the DSM increases, so does the cost for the hardware support needed for it. | ||
Revision as of 21:13, 18 April 2011
This article discusses the design of scalable shared memory multiprocessors. As we know, bus-based multiprocessor possess the disadvantage of being non-scalable. So, a new system called Distributed Shared Memory was introduced wherein, accessing different parts of memory takes different times. Thus, a DSM is more scalable than a bus-based multiprocessors. But as the size of the DSM increases, so does the cost for the hardware support needed for it.
The wiki chapter introduces the approaches used to scale multiprocessors, the cache coherence protocols for a basic DSM and explains how the race conditions are handled.