CSC/ECE 506 Fall 2007/wiki 2 5 2281: Difference between revisions
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Cache sizes in multicore architectures Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs. <br> | Cache sizes in multicore architectures Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs. <br> | ||
{| border="1" cellspacing="0" cellpadding=" | {| border="1" cellspacing="0" cellpadding="100" align="center" | ||
! Multi-core Architecture | ! Multi-core Architecture | ||
! Number of levels | ! Number of levels | ||
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! Coherence Protocol used | ! Coherence Protocol used | ||
|- | |- | ||
| AMD Opteron Processor | | AMD Opteron Processor | ||
| 2 | | 2 | ||
Revision as of 23:13, 24 September 2007
Objective
Cache sizes in multicore architectures Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.
| Multi-core Architecture | Number of levels | Line Size | Cache Size | Associativity | Latency | Is the Level shared | Coherence Protocol used |
|---|---|---|---|---|---|---|---|
| AMD Opteron Processor | 2 | - | 64 Byte L1, 1024 KByte L2 | 2 Way Associative ECC Protected L1 Data; 16 Way Associative L2 Cache | Two 64 bit operations per 3 cycle latency | No | Exclusive cache architecture |
| with | row2 | with | row2 | with | row2 | with | row2 |