CSC/ECE 506 Spring 2011/6a ms

Cache Architecture

CPU caches are designed to mitigate the performance hit of reading and writing to main memory. Since main memory clock speeds are typically much slower than processor clock speeds, going to main memory for every read and write can result in a very slow system. Caches are constructed on the processor chip and take advantage of spatial and temporal locality to store data likely to be needed again by the processor.

Modern processors typically have two to three levels of cache. Each processor core has private level 1 (L1) data and instruction caches and a L2 combined data+instruction cache. Sometimes, a shared L3 cache is used to serve as an additional buffer between the cache and main memory. The figure below shows the cache hierarchy in a modern processor.

Intel's Nehalem architecture, used on their core i7 processors

To give an idea of typical cache sizes, examples of modern processor caches are given in the table below.

Modern cache structures

Vendor and Processor	Cores	L1 cache	L2 cache	L3 cache	Date
Intel Pentium Dual Core	2	I: 32KB D: 32KB	1MB 8-way set-associative
row 2, cell 1	row 2, cell 2	row 2, cell 3
row 3, cell 1	row 3, cell 2	row 3, cell 3