CSC/ECE 506 Fall 2007/wiki2 05 sa: Difference between revisions

From Expertiza_Wiki
Jump to navigation Jump to search
No edit summary
No edit summary
Line 7: Line 7:
recent single-core designs.
recent single-core designs.


{| border="1" cellspacing="0"  
 
cellpadding="5" align="center"
{| border="1" cellpadding="5" cellspacing="0" align="center"
!<center>Multicore Processors</center>
|+'''Detail of Caches'''
|-
! colspan="5" style="background:#ffdead;" | Multicore Processors
|-
|-
! Processor Name
! Processor Name
! Number of levels
! Number of Levels
! Line size
! Line Size
! Size
! Size
! Coherence Protocol
! Coherence Protocol
|-  
|-
| a
|-
| table
! colspan="5" style="background:#ffdead;" | Singlecore Processors
|-
| colspan="5" style="border-bottom:3px solid grey;" align="center" | Bottom
|-
|-
|}
|}

Revision as of 16:55, 24 September 2007

Cache sizes in multicore architectures

Topic - Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.


Detail of Caches
Multicore Processors
Processor Name Number of Levels Line Size Size Coherence Protocol
Singlecore Processors
Bottom
Retrieved from "https://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Fall_2007/wiki2_05_sa&oldid=4354"