CSC/ECE 506 Fall 2007/wiki2 05 sa: Difference between revisions
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is shared, and coherence protocol used. Compare this with two or three | is shared, and coherence protocol used. Compare this with two or three | ||
recent single-core designs. | recent single-core designs. | ||
{| border="1" cellspacing="0" | |||
cellpadding="5" align="center" | |||
!<center>Multicore Processors</center> | |||
|- | |||
! Processor Name | |||
! Number of levels | |||
! Line size | |||
! Size | |||
! Coherence Protocol | |||
|- | |||
| a | |||
| table | |||
|- | |||
|} | |||
Revision as of 16:31, 24 September 2007
Cache sizes in multicore architectures
Topic - Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.
cellpadding="5" align="center"| Processor Name | Number of levels | Line size | Size | Coherence Protocol |
|---|---|---|---|---|
| a | table |