CSC/ECE 506 Fall 2007/wiki 2 5 2281: Difference between revisions

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== Objective ==
== Objective ==
Cache sizes in multicore architectures Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.
Cache sizes in multicore architectures Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs. <br>
 
{| border="1" cellspacing="0" cellpadding="10" align="center"
! Multi-core Architecture
! Number of levels
! Line Size
! Cache Size
! Associativity
! Latency
! Is the Level shared
! Coherence Protocol used
|-
| a
| table
| a
| table
| a
| table
| a
| table
|-
| with
| row2
| with
| row2
| with
| row2
| with
| row2
|-
|}

Revision as of 23:48, 23 September 2007

Objective

Cache sizes in multicore architectures Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.

Multi-core Architecture Number of levels Line Size Cache Size Associativity Latency Is the Level shared Coherence Protocol used
a table a table a table a table
with row2 with row2 with row2 with row2
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