CSC/ECE 506 Spring 2010/Ch 9/Synchronization: Difference between revisions
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===Hardware Implementations=== | ===Hardware Implementations=== | ||
Hardware implementations for synchronization traditionally include locks, barriers, and mutual exclusion. These types of hardware synchronizations use a method called busy-waiting, or spinning | Hardware implementations for synchronization traditionally include locks, barriers, and mutual exclusion. These types of hardware synchronizations use a method called busy-waiting, or spinning which prevents threads from continuing to execute. Spinning simply means that a thread continuously checks if it is okay to continue (threads are usually competing with each other). This technique is implemented in hardware through mutexes or semaphore, which prevent multiple processes from being accessed at the same time. | ||
Atomic instructions, which are support by the processor Instruction Set Architecture(ISA), are typically used for hardware synchronizations. Some of these atomic instructions include: Test-and-Set, Fetch-and-Increment, Test-and- Test-and-Set. | |||
===OS Implementations=== | ===OS Implementations=== | ||
Revision as of 14:16, 12 April 2010
Hardware Support For Synchronization
Hardware Implementations
Hardware implementations for synchronization traditionally include locks, barriers, and mutual exclusion. These types of hardware synchronizations use a method called busy-waiting, or spinning which prevents threads from continuing to execute. Spinning simply means that a thread continuously checks if it is okay to continue (threads are usually competing with each other). This technique is implemented in hardware through mutexes or semaphore, which prevent multiple processes from being accessed at the same time.
Atomic instructions, which are support by the processor Instruction Set Architecture(ISA), are typically used for hardware synchronizations. Some of these atomic instructions include: Test-and-Set, Fetch-and-Increment, Test-and- Test-and-Set.