Chp8 my: Difference between revisions
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4. Invalid (I): the cache block is invalid. | 4. Invalid (I): the cache block is invalid. | ||
[[Image:MESI.jpg]] | |||
====Intel==== | ====Intel==== | ||
Revision as of 01:08, 26 March 2010
In computing, cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.
Cache Coherence
Definition
Coherency protocol
MSI protocol
Intel
AMD
MESI protocol
In MESI protocol, there are four cache block status: 1. Modified (M): the cache block valid in only one cache and the value is like different from the main memory. 2. Exclusive (E): the cache block is valid and clean, but only resides in one cache. 3. Shared (S): the cache block is valid and clean, but may exist in multiple caches. 4. Invalid (I): the cache block is invalid.
Intel
AMD
MOESI protocol
Intel
AMD
AMD Opteron is using MOESI protocol for cache sharing.
