Chp8 my: Difference between revisions
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<li>[http://www.csd.uoc.gr/~poisson/courses/CSD-527-report-engl.pdf Trace-Driven Simulation of the MSI, MESI and Dragon Cache Coherence Protocols]</li> | <li>[http://www.csd.uoc.gr/~poisson/courses/CSD-527-report-engl.pdf Trace-Driven Simulation of the MSI, MESI and Dragon Cache Coherence Protocols]</li> | ||
<li>[http://www.chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html Understanding the Detailed Architecture of AMD's 64 bit Core]</li> | <li>[http://www.chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html Understanding the Detailed Architecture of AMD's 64 bit Core]</li> | ||
<li>[http://www.wiki.cl.cam.ac.uk/rowiki/CompArch/ACS-CMP/Seminar4 MSI,MESI,MOESI sheet]</li> | |||
</ol> | </ol> | ||
Revision as of 00:47, 26 March 2010
In computing, cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.