Chp8 my: Difference between revisions
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<li>[http://techreport.com/articles.x/8236/2 A closer look at AMD's dual-core architecture]</li> | <li>[http://techreport.com/articles.x/8236/2 A closer look at AMD's dual-core architecture]</li> | ||
<li>[http://www.seas.upenn.edu/~cse400/CSE400_2008_2009/related_work.pdf CSE 400 – Related Work: Instructions & Example]</li> | <li>[http://www.seas.upenn.edu/~cse400/CSE400_2008_2009/related_work.pdf CSE 400 – Related Work: Instructions & Example]</li> | ||
<li>[http://www.csd.uoc.gr/~poisson/courses/CSD-527-report-engl.pdf Trace-Driven Simulation of the MSI, MESI and Dragon Cache Coherence Protocols]</li> | |||
</ol> | </ol> | ||
Revision as of 19:21, 17 March 2010
In computing, cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.
Cache Coherence
Definition
Coherency protocol
MSI protocol
MESI protocol
Intel is using this