CSC/ECE 506 Fall 2007/wiki1 10 mt: Difference between revisions
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Dataflow and systolic are two of the many possible parallel computer architectures. Unlike [http://en.wikipedia.org/wiki/Shared_memory shared address], [http://en.wikipedia.org/wiki/Message_passing message passing] and [http://en.wikipedia.org/wiki/Data_parallelism data parallel processing], the dataflow and systolic architectures were not as commonly used for parallel programming systems although they recieved a considerable amount of analysis from both private industry and academia. | Dataflow and systolic are two of the many possible parallel computer architectures. Unlike [http://en.wikipedia.org/wiki/Shared_memory shared address], [http://en.wikipedia.org/wiki/Message_passing message passing] and [http://en.wikipedia.org/wiki/Data_parallelism data parallel processing], the dataflow and systolic architectures were not as commonly used for parallel programming systems although they recieved a considerable amount of analysis from both private industry and academia. | ||
Dataflow architecture is in oppostion to the von Neumann or control flow architecture which has memory, and I/O subsystem, an arithmetic unit and a control unit. The one shared memory is used for both program instructions and data with a data bus and address bus between the memory and processing unit. Because instructions and data must be fetched in sequential order, a bottleneck may occur limiting the throughput between the CPU and the memory. | Dataflow architecture is in oppostion to the [ http://en.wikipedia.org/wiki/Von_Neumann_architecture von Neumann ] or control flow architecture which has memory, and I/O subsystem, an arithmetic unit and a control unit. The one shared memory is used for both program instructions and data with a data bus and address bus between the memory and processing unit. Because instructions and data must be fetched in sequential order, a bottleneck may occur limiting the throughput between the CPU and the memory. | ||
=== New Developments in Dataflow and Systolic Architectures === | === New Developments in Dataflow and Systolic Architectures === | ||
Revision as of 12:37, 3 September 2007
Dataflow & Systolic Architectures
Dataflow and systolic are two of the many possible parallel computer architectures. Unlike shared address, message passing and data parallel processing, the dataflow and systolic architectures were not as commonly used for parallel programming systems although they recieved a considerable amount of analysis from both private industry and academia.
Dataflow architecture is in oppostion to the [ http://en.wikipedia.org/wiki/Von_Neumann_architecture von Neumann ] or control flow architecture which has memory, and I/O subsystem, an arithmetic unit and a control unit. The one shared memory is used for both program instructions and data with a data bus and address bus between the memory and processing unit. Because instructions and data must be fetched in sequential order, a bottleneck may occur limiting the throughput between the CPU and the memory.