CSC 456 Fall 2013/1c wa: Difference between revisions

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''' Memory Standards: '''
{|border=1


 
    | Standard
 
    | Mem Clock
    | Cycle time
    | I/O Bus Clock
    | Module Name
    | Peak Transfer Rate
    | Prefetch
    |-
    | DDR2-400
    | 100MHz
    | 10 ns
    | 200 MHz
    | PC2-3200
    | 3200 MB/s
    | 4 n
    |-
    | DDR2-533
    | 133 MHz
    | 7.5 ns
    | 266
    | PC2-4200
    | 4266 MB/s
| 4 n
    |-
    | DDR2-667
    | 166 MHz
    | 6 ns
    | 333 MHz
    | PC2-5300
    | 5333 MB/s
    | 4 n
    |-
    | DDR2-800
    | 200 MHz
    | 5 ns
    | 400 MHz
    | PC2-6400
    | 6400 MB/s
    | 4 n
    |-
    | DDR2-1066
    | 266 MHz
    | 3.75 ns
    | 533 MHz
    | PC2-8500
    | 8533 MB/s
    | 4 n
    |-
    | DDR3-800
    | 100 MHz
    | 10 ns
    | 400 MHz
    | PC2-6400
    | 6400 MB/s
    | 8 n
    |-
    | DDR3-1066
    | 133 MHz
    | 7.5 ns
    | 533 MHz
    | PC2-8500
    | 8533 MB/s
    | 8 n
    |-
    | DDR3-1333
    | 166 MHz
    | 6 ns
    | 667 MHz
    | PC2-10600
    | 10667 MB/s
    | 8 n
    |-
    | DDR3-1600
    | 200 MHz
    | 5 ns
    | 800 MHz
    | PC2-12800
    | 12800 MB/s
    | 8 n
    |}
<br />


'''L1 & L2 cache'''
'''L1 & L2 cache'''
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References<br />
References<br />
[http://download.intel.com/design/itanium2/manuals/25111003.pdf Itanium Specs(p.20)]<br />
[http://download.intel.com/design/itanium2/manuals/25111003.pdf Itanium Specs(p.20)]<br />
[http://www.chips.5u.com/idxhst.html Ref1]<br />
[http://www.chips.5u.com/idxhst.html Pentium Pro]<br />
[http://en.wikipedia.org/wiki/List_of_Intel_microprocessors Intel Processors]<br />
[http://en.wikipedia.org/wiki/List_of_Intel_microprocessors Intel Processors]<br />
[http://en.wikipedia.org/wiki/Intel_80486 First on-board L1]<br />
[http://en.wikipedia.org/wiki/Intel_80486 First on-board L1]<br />
[http://faculty.washington.edu/lcrum/Archives/TCSS372AS07/Slides04_05.ppt Cache Trend Table‎]<br />
[http://faculty.washington.edu/lcrum/Archives/TCSS372AS07/Slides04_05.ppt Cache Trend Table‎]<br />
[http://www.eecs.berkeley.edu/Pubs/TechRpts/1999/CSD-99-1034.pdf Sector Caches]<br />
[http://www.eecs.berkeley.edu/Pubs/TechRpts/1999/CSD-99-1034.pdf Sector Caches]<br />
[http://www.tomshardware.com/reviews/ram-speed-tests,1807-3.html DDR2/3 Speeds] <br />
[http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf Memory Wall] <br />

Revision as of 20:12, 25 September 2013

Trends in cache size and organization

Task 1c. Trends in cache size and organization Over the years, caches have grown larger--up to a point, and then L1 caches tended for awhile to decrease in size. Why? In the early 1980s, associativity increased; beginning about 1990, it decreased, and then by about 2000, it was increasing again. Why? When was the first machine with an L2 cache? An L3 cache? How fast were the various levels of caches, and how did this speed compare to main memory? There is a wealth of information to bring to bear on this topic.


To-Do:
find first L3 and fill in
order the list by year
analyze: average cc speed for a given level, main mem cc speed evolution


Theory: Cache Associativity decreased as cache size became larger because it became too expensive to have to search the cache each time once the cache was too large. Also, bigger the cache size as a percentage of main memory, the less need for associativity. But while caches and main memory have both grown, main memory size has grown faster in the 2000’s. So when the percentage of cache to main memory goes down associativity needs to increase.


The Pentium/Pentium (1995)pro was the first processor to have the l2 cache on the processor chip. Before this, the l2 cache was an option to add on to the motherboard. [1]

Systems to consider in table

Pentium
amd
Mips
sun-microsystems: sparc
ibm: power pc
DEC: alpha

Penalty <100 when before 2000 after 2000 started to increase to get to main memory
< 20 1 level fine
<=100 2 level
>=200 3 level

miss rate reported, spec benchmarks >=200 3 level

miss rate reported, spec benchmarks


Memory Standards:

Standard Mem Clock Cycle time I/O Bus Clock Module Name Peak Transfer Rate Prefetch
DDR2-400 100MHz 10 ns 200 MHz PC2-3200 3200 MB/s 4 n
DDR2-533 133 MHz 7.5 ns 266 PC2-4200 4266 MB/s 4 n
DDR2-667 166 MHz 6 ns 333 MHz PC2-5300 5333 MB/s 4 n
DDR2-800 200 MHz 5 ns 400 MHz PC2-6400 6400 MB/s 4 n
DDR2-1066 266 MHz 3.75 ns 533 MHz PC2-8500 8533 MB/s 4 n
DDR3-800 100 MHz 10 ns 400 MHz PC2-6400 6400 MB/s 8 n
DDR3-1066 133 MHz 7.5 ns 533 MHz PC2-8500 8533 MB/s 8 n
DDR3-1333 166 MHz 6 ns 667 MHz PC2-10600 10667 MB/s 8 n
DDR3-1600 200 MHz 5 ns 800 MHz PC2-12800 12800 MB/s 8 n


L1 & L2 cache

System Year L1 Size (cache) L1 Speed (cc) L1 Associativity L2 Size L2 Speed L2 Associativity L2 On-Chip? L3 Size L3 Speed L3 Associativity L3 On-Chip? Main Mem Penalty (cc) Notes:
IBM 360/85 1968 16 - 32 KB ? Sector None N/A N/A N/A None N/A N/A N/A ? First processor with a cache, clock speed 12.5MHz
IBM 486 1989 8 kb ? L1 Associativity 256 kb no
Intel 80486 1989 8 KB ? 4-way associative None N/A N/A N/A None N/A N/A N/A ? First processor with a cache, clock speed 12.5MHz
SuperSPARC ?/1992 (16+20) KB ? 4 & 5 way set 0 - 2 MB ? ? No N/A ? Used to render Toy Story, Core @ 40MHz
Alpha 21064(DEC) 09/1992 (8+8) KB 1 Direct 128kb - 16mb 3-16 cc Direct No N/A 8 cc
UltraSPARC 06/1995 (16+16) KB 1 2-Way & Direct 512KB - 4MB 1, pipe=3 Direct No N/A 2-3 64-bit w/ Core@200MHz
Alpha 21164(DEC) 01/1995 (8+8) KB 1 Direct 96 Kb 2 3 way set Yes ?
K6-III 1999 32 kib 100 mhz 2 way 256 kib 100 mhz 4 way yes 1 mb no
Pentium 4 10/2000 8 KB (trace) 2 4 Way 256KB full speed 8 Way Yes None 4 (Mem controller)
UltraSPARC III ?/2001 (32+64) KB 1 4 Way 2-8MB 2-3 ? No 4 (Mem controller)
Itanium 2 2002 16 KB 1 4 -way 256KB 5 8-way yes 3 MB 12 12 way (4 per MB) Yes ?


References
Itanium Specs(p.20)
Pentium Pro
Intel Processors
First on-board L1
Cache Trend Table‎
Sector Caches
DDR2/3 Speeds
Memory Wall

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