CSC/ECE 506 Spring 2012/preface: Difference between revisions
Jump to navigation
Jump to search
| Line 1: | Line 1: | ||
= Preface = | = Preface = | ||
== Chapter | = Chapter 1: Perspectives = | ||
== Chapter 1: ''Supercomputer comparisons'' == | |||
== Chapter 1b: ''Does Moore's Law still hold?'' == | == Chapter 1b: ''Does Moore's Law still hold?'' == | ||
== Chapter 1c: ''MISD architectures'' == | == Chapter 1c: ''MISD architectures'' == | ||
= Chapter 2: Parallel Programming Models | |||
== Chapter 2a: ''SAS programming on distributed-memory machines'' == | == Chapter 2a: ''SAS programming on distributed-memory machines'' == | ||
== Chapter 2b: ''Data parallelism in GPUs'' == | == Chapter 2b: ''Data parallelism in GPUs'' == | ||
=Chapter 3: Shared Memory Parallel Programming+ | |||
== Chapter 3a: ''Patterns of parallel programming'' == | == Chapter 3a: ''Patterns of parallel programming'' == | ||
== Chapter 3b: '' Map Reduce'' == | == Chapter 3b: '' Map Reduce'' == | ||
=Chapter 4: Issues in Shared Memory Programming= | |||
== Chapter 4a: ''Automatic parallelism and its limitations'' == | == Chapter 4a: ''Automatic parallelism and its limitations'' == | ||
== Chapter 4b: ''The limits to speedup'' == | == Chapter 4b: ''The limits to speedup'' == | ||
=Chapter 5:Parallel Programming for Linked Data Structures= | |||
== Chapter 5a: '' Other linked data structures '' == | == Chapter 5a: '' Other linked data structures '' == | ||
=Chapter 6: Introduction to Memory Hierarchy Organization= | |||
== Chapter 6b: ''Multiprocessor issues with write buffers'' == | == Chapter 6b: ''Multiprocessor issues with write buffers'' == | ||
=Chapter 7:Introduction to Shared Memory Multiprocessors+ | |||
== Chapter 7b: '' TLB coherence'' == | == Chapter 7b: '' TLB coherence'' == | ||
=Chapter 8: Bus-Based Coherent Multiprocessors | |||
== Chapter 8a: ''MSI, MESI, MESIF, and MOESI protocols on real architectures'' == | == Chapter 8a: ''MSI, MESI, MESIF, and MOESI protocols on real architectures'' == | ||
== Chapter 8b: ''8b. Update and adaptive coherence protocols on real architectures, and power considerations'' == | == Chapter 8b: ''8b. Update and adaptive coherence protocols on real architectures, and power considerations'' == | ||
=Chapter 9: Hardware Support for Synchronization= | |||
== Chapter 9a: ''Reducing locking overhead''== | == Chapter 9a: ''Reducing locking overhead''== | ||
=Chapter 10: Memory Consistency Models= | |||
== Chapter 10a: '' Prefetching and consistency models'' == | == Chapter 10a: '' Prefetching and consistency models'' == | ||
== Chapter 10b: '' Use of consistency models in current multiprocessors'' == | == Chapter 10b: '' Use of consistency models in current multiprocessors'' == | ||
=Chapter 11: Distributed Shared Memory Multiprocessors= | |||
== Chapter 11a: ''Performance of DSM systems'' == | == Chapter 11a: ''Performance of DSM systems'' == | ||
== Chapter 11b: ''Improvements to directory-based cache-coherence animations'' == | == Chapter 11b: ''Improvements to directory-based cache-coherence animations'' == | ||
=Chapter 12: Interconnection Network Architecture= | |||
== Chapter 12a: ''New interconnection topologies'' == | == Chapter 12a: ''New interconnection topologies'' == | ||
== Chapter 12b: ''On-chip interconnects'' == | == Chapter 12b: ''On-chip interconnects'' == | ||
=References= | =References= | ||
<references/> | <references/> | ||
Revision as of 16:51, 15 April 2012
Preface
Chapter 1: Perspectives
Chapter 1: Supercomputer comparisons
Chapter 1b: Does Moore's Law still hold?
Chapter 1c: MISD architectures
= Chapter 2: Parallel Programming Models
Chapter 2a: SAS programming on distributed-memory machines
Chapter 2b: Data parallelism in GPUs
=Chapter 3: Shared Memory Parallel Programming+
Chapter 3a: Patterns of parallel programming
Chapter 3b: Map Reduce
Chapter 4a: Automatic parallelism and its limitations
Chapter 4b: The limits to speedup
Chapter 5:Parallel Programming for Linked Data Structures
Chapter 5a: Other linked data structures
Chapter 6: Introduction to Memory Hierarchy Organization
Chapter 6b: Multiprocessor issues with write buffers
=Chapter 7:Introduction to Shared Memory Multiprocessors+
Chapter 7b: TLB coherence
=Chapter 8: Bus-Based Coherent Multiprocessors
Chapter 8a: MSI, MESI, MESIF, and MOESI protocols on real architectures
Chapter 8b: 8b. Update and adaptive coherence protocols on real architectures, and power considerations
Chapter 9: Hardware Support for Synchronization
Chapter 9a: Reducing locking overhead
Chapter 10: Memory Consistency Models
Chapter 10a: Prefetching and consistency models
Chapter 10b: Use of consistency models in current multiprocessors
Chapter 11a: Performance of DSM systems
Chapter 11b: Improvements to directory-based cache-coherence animations
Chapter 12: Interconnection Network Architecture
Chapter 12a: New interconnection topologies
Chapter 12b: On-chip interconnects
References
<references/>