CSC/ECE 506 Spring 2012/8a cj: Difference between revisions
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intuition, and aesthetics of the designers, and the science is workload-driven evaluation." [http://books.google.com/books?id=MHfHC4Wf3K0C&pg=PA620&lpg=PA620&dq=Culler+and+Singh+1998&source=bl&ots=1KHO-a3JXQ&sig=ZEZ0Xjer6Y4IJJgm6GXjnerYnkI&hl=en&sa=X&ei=ko9oT4LfH4aPsQKItY2wCQ&ved=0CCsQ6AEwAQ#v=onepage&q=Culler%20and%20Singh%201998&f=false] | intuition, and aesthetics of the designers, and the science is workload-driven evaluation." [http://books.google.com/books?id=MHfHC4Wf3K0C&pg=PA620&lpg=PA620&dq=Culler+and+Singh+1998&source=bl&ots=1KHO-a3JXQ&sig=ZEZ0Xjer6Y4IJJgm6GXjnerYnkI&hl=en&sa=X&ei=ko9oT4LfH4aPsQKItY2wCQ&ved=0CCsQ6AEwAQ#v=onepage&q=Culler%20and%20Singh%201998&f=false] | ||
While making definitive design decisions for machine designed to run a variety of programs is challenging, the performance of various cache parameters for specific programs can be simulated allowing for the prediction of general trends. Figure 5 shows the performance of the MESI protocol (III) and the standard MSI 3 | While making definitive design decisions for machine designed to run a variety of programs is challenging, the performance of various cache parameters for specific programs can be simulated allowing for the prediction of general trends. Figure 5 shows the performance of the MESI protocol (III) and the standard MSI 3 state protocol (3st). The MSI protocol when BusRdX instead of BusUpgr is used for S -> M transitions is also shown (3st-RdX) | ||
[[Image:ProtocolTraffic.jpg|thumb|upright|center|450px|<b>Figure 5:</b> Traffic for various protocols [http://ams.ict.ac.cn/wp-content/uploads/2012/03/Parallel-computer-architecture.pdf]]] | [[Image:ProtocolTraffic.jpg|thumb|upright|center|450px|<b>Figure 5:</b> Traffic for various protocols [http://ams.ict.ac.cn/wp-content/uploads/2012/03/Parallel-computer-architecture.pdf]]] | ||
[[Image:TypeOfMiss.jpg|thumb|upright|center|800px|<b>Figure 6:</b> Type of Miss [http://ams.ict.ac.cn/wp-content/uploads/2012/03/Parallel-computer-architecture.pdf]]] | [[Image:TypeOfMiss.jpg|thumb|upright|center|800px|<b>Figure 6:</b> Type of Miss [http://ams.ict.ac.cn/wp-content/uploads/2012/03/Parallel-computer-architecture.pdf]]] | ||
=References= | =References= | ||
# [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1 The research of the inclusive cache used in multi-core processor] | # [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1 The research of the inclusive cache used in multi-core processor] | ||
# [http://books.google.com/books?id=MHfHC4Wf3K0C&pg=PA620&lpg=PA620&dq=Culler+and+Singh+1998&source=bl&ots=1KHO-a3JXQ&sig=ZEZ0Xjer6Y4IJJgm6GXjnerYnkI&hl=en&sa=X&ei=ko9oT4LfH4aPsQKItY2wCQ&ved=0CCsQ6AEwAQ#v=onepage&q=Culler%20and%20Singh%201998&f=false Parallel Computer Architecture: A Hardware/Software Approach] | # [http://books.google.com/books?id=MHfHC4Wf3K0C&pg=PA620&lpg=PA620&dq=Culler+and+Singh+1998&source=bl&ots=1KHO-a3JXQ&sig=ZEZ0Xjer6Y4IJJgm6GXjnerYnkI&hl=en&sa=X&ei=ko9oT4LfH4aPsQKItY2wCQ&ved=0CCsQ6AEwAQ#v=onepage&q=Culler%20and%20Singh%201998&f=false Parallel Computer Architecture: A Hardware/Software Approach] | ||
Revision as of 14:33, 20 March 2012
MSI, MESI, MESIF, and MOESI protocols on real architectures
MSI Protocol
MESI Protocol
Five State Protocols
MOESI
MESIF
Protocol Performance
Protocol performance is strongly linked to the program that is running on the parallel system. This complicates protocol performance evaluation and prevents the designer from definitively choosing the best protocol. This binding of program and protocol makes "Making design decisions in real systems ... part art and part science. The art is the past experience, intuition, and aesthetics of the designers, and the science is workload-driven evaluation." [4]
While making definitive design decisions for machine designed to run a variety of programs is challenging, the performance of various cache parameters for specific programs can be simulated allowing for the prediction of general trends. Figure 5 shows the performance of the MESI protocol (III) and the standard MSI 3 state protocol (3st). The MSI protocol when BusRdX instead of BusUpgr is used for S -> M transitions is also shown (3st-RdX)
