CSC/ECE 506 Spring 2012/8a cj: Difference between revisions

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[[Image:MESIFVMESI.jpg|thumb|upright|center|450px|<b>Figure 4:</b> Reduced Traffic with MESIF Protocol [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1]]]
[[Image:MESIFVMESI.jpg|thumb|upright|center|450px|<b>Figure 4:</b> Reduced Traffic with MESIF Protocol [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1]]]
=Protocol Performance=
=Protocol Performance=
[[Image:ProtocolTraffic.jpg|thumb|upright|center|450px|<b>Figure 5:</b> Traffic for various protocols [http://ams.ict.ac.cn/wp-content/uploads/2012/03/Parallel-computer-architecture.pdf]]]
[[Image:TypeOfMiss.jpg|thumb|upright|center|450px|<b>Figure 5:</b> Type of Miss [http://ams.ict.ac.cn/wp-content/uploads/2012/03/Parallel-computer-architecture.pdf]]]
[[Image:TypeOfMiss.jpg|thumb|upright|center|450px|<b>Figure 5:</b> Type of Miss [http://ams.ict.ac.cn/wp-content/uploads/2012/03/Parallel-computer-architecture.pdf]]]
=References=
=References=
# [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1 The research of the inclusive cache used in multi-core processor]
# [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4606981&tag=1 The research of the inclusive cache used in multi-core processor]
# [http://books.google.com/books?id=MHfHC4Wf3K0C&pg=PA620&lpg=PA620&dq=Culler+and+Singh+1998&source=bl&ots=1KHO-a3JXQ&sig=ZEZ0Xjer6Y4IJJgm6GXjnerYnkI&hl=en&sa=X&ei=ko9oT4LfH4aPsQKItY2wCQ&ved=0CCsQ6AEwAQ#v=onepage&q=Culler%20and%20Singh%201998&f=false]
# [http://books.google.com/books?id=MHfHC4Wf3K0C&pg=PA620&lpg=PA620&dq=Culler+and+Singh+1998&source=bl&ots=1KHO-a3JXQ&sig=ZEZ0Xjer6Y4IJJgm6GXjnerYnkI&hl=en&sa=X&ei=ko9oT4LfH4aPsQKItY2wCQ&ved=0CCsQ6AEwAQ#v=onepage&q=Culler%20and%20Singh%201998&f=false Parallel Computer Architecture: A Hardware/Software Approach]

Revision as of 14:10, 20 March 2012

MSI, MESI, MESIF, and MOESI protocols on real architectures

MSI Protocol

Figure 1: MSI State Diagram

MESI Protocol

Figure 2: MESI State Diagram

Five State Protocols

MOESI

Figure 3: MOESI State Diagram

MESIF

Figure 4: Reduced Traffic with MESIF Protocol [1]

Protocol Performance

Figure 5: Traffic for various protocols [2]
Figure 5: Type of Miss [3]

References

  1. The research of the inclusive cache used in multi-core processor
  2. Parallel Computer Architecture: A Hardware/Software Approach
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