CSC/ECE 506 Spring 2010/8a sk: Difference between revisions
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= MSI = | = MSI = | ||
MSI protocol is a three-state write-back invalidation protocol which is one of the simplest and earliest-used snooping-based cache coherence-protocols. According to this protocol, a cache block can be in one of the Modified (M), Shared (S), and Invalid (I) states. | |||
The '''Modified''' state indicates that the variable in the cache has been modified and therefore has a different value from that found in the main memory. A cache line in this state thus needs to be written back to the block to memory during eviction. | |||
The '''Shared''' state indicates that the block exists in one or more caches, and is clean, implying that its value is consistent with the one in main memory. So a cache block in this state can be evicted without having to write it back to the main memory. | |||
The '''Invalid''' state indicates that the cache block is invalid. | |||
In MSI protocol, processor requests to the cache include: | |||
1. PrRd: Processor requests read to a cache block. | |||
2. PrWr: Processor requests write to a cache block. | |||
In MSI protocol Bus-side requests include: | |||
1. BusRd: BusRd transaction is generated by a PrRd that misses in the cache, and the processor expects a data response as a result. The cache controller puts the address on the bus and asks for a copy that it does not intend to modify. The memory supplies the data. | |||
2. BusRdX: BusRdX transaction is generated by a PrWr to a block that is either not in the cache or is in the cache but is not in modified state. The cache controller puts the address on the bus and asks for an exclusive copy that it intends to modify. The memory system provides the data. All other caches are invalidated. Once the cache obtains the exclusive copy, the write can be performed in the cache. | |||
3. Flush: Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor. | |||
= MESI = | = MESI = | ||
Revision as of 00:17, 19 March 2012
Introduction
MSI
MSI protocol is a three-state write-back invalidation protocol which is one of the simplest and earliest-used snooping-based cache coherence-protocols. According to this protocol, a cache block can be in one of the Modified (M), Shared (S), and Invalid (I) states. The Modified state indicates that the variable in the cache has been modified and therefore has a different value from that found in the main memory. A cache line in this state thus needs to be written back to the block to memory during eviction. The Shared state indicates that the block exists in one or more caches, and is clean, implying that its value is consistent with the one in main memory. So a cache block in this state can be evicted without having to write it back to the main memory. The Invalid state indicates that the cache block is invalid.
In MSI protocol, processor requests to the cache include: 1. PrRd: Processor requests read to a cache block. 2. PrWr: Processor requests write to a cache block.
In MSI protocol Bus-side requests include: 1. BusRd: BusRd transaction is generated by a PrRd that misses in the cache, and the processor expects a data response as a result. The cache controller puts the address on the bus and asks for a copy that it does not intend to modify. The memory supplies the data. 2. BusRdX: BusRdX transaction is generated by a PrWr to a block that is either not in the cache or is in the cache but is not in modified state. The cache controller puts the address on the bus and asks for an exclusive copy that it intends to modify. The memory system provides the data. All other caches are invalidated. Once the cache obtains the exclusive copy, the write can be performed in the cache. 3. Flush: Flush is a snooped request that indicates that an entire cache block is written back to the main memory by another processor.