Chapter 6: Joshua Mohundro, Patrick Wong: Difference between revisions
Jump to navigation
Jump to search
m (→Cache) |
m (→Victim Cache) |
||
| Line 3: | Line 3: | ||
== Victim Cache == | == Victim Cache == | ||
The Victim Cache, in architectures with them, stores just-evicted lines from another level of cache. For speed reasons, this cache is usually direct-mapped and has very few entries, but solves one of the pathological cases for direct-mapped caches, the | The Victim Cache, in architectures with them, stores just-evicted lines from another level of cache. For speed reasons, this cache is usually direct-mapped and has very few entries, but solves one of the pathological cases for direct-mapped caches, the alternating memory access pattern (of which a cache line conflict occurs). In effect, this extends the associativity of would-be conflict misses by an extra way for very low cost. | ||
Architectures implementing victim cache for x86 include the AMD K7, K8, and finally K10 (a variant of K8). The Transmeta Efficeon also implemented a victim cache. | Architectures implementing victim cache for x86 include the AMD K7, K8, and finally K10 (a variant of K8). The Transmeta Efficeon also implemented a victim cache. | ||
Revision as of 18:38, 30 January 2012
Sectored Cache
Hard section
Victim Cache
The Victim Cache, in architectures with them, stores just-evicted lines from another level of cache. For speed reasons, this cache is usually direct-mapped and has very few entries, but solves one of the pathological cases for direct-mapped caches, the alternating memory access pattern (of which a cache line conflict occurs). In effect, this extends the associativity of would-be conflict misses by an extra way for very low cost.
Architectures implementing victim cache for x86 include the AMD K7, K8, and finally K10 (a variant of K8). The Transmeta Efficeon also implemented a victim cache.