CSC/ECE 506 Spring 2012/1c 12: Difference between revisions

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[http://www.ece.ncsu.edu/people/solihin Dr. Yan Solihin] defines MISD as "..an architecture in which multiple processing elements execute from different instruction streams, and data is passed from one processing element to the next."[[#References|<sup>[2]</sup>]] He also notes that MISD architectures are restricted to certain types of computations due to the requirement of data-passing between processing elements.[[#References|<sup>[2]</sup>]]  Each processing element executes different instructions on the data stream.[[#References|<sup>[3]</sup>]]  Every time the data is processed by a processing element, we can always argu that the data is no longer the original data introduced at the start of the stream.[[#References|<sup>[4]</sup>]]  
[http://www.ece.ncsu.edu/people/solihin Dr. Yan Solihin] defines MISD as "..an architecture in which multiple processing elements execute from different instruction streams, and data is passed from one processing element to the next."[[#References|<sup>[2]</sup>]] He also notes that MISD architectures are restricted to certain types of computations due to the requirement of data-passing between processing elements.[[#References|<sup>[2]</sup>]]  Each processing element executes different instructions on the data stream.[[#References|<sup>[3]</sup>]]  Every time the data is processed by a processing element, we can always argu that the data is no longer the original data introduced at the start of the stream.[[#References|<sup>[4]</sup>]]  


[[image:Misd Arch Solihin2.jpg|thumb|center|400px|alt=MISD computer architecture outline.|From NCSU CSC/ECE 506 Spring 2012 Lecture 1 notes[[#References|<sup>[5]</sup>]]. From the image, we see that the data stream has one clear entrance and exit into the system.  Each processing element has access to a collective and/or individual instruction cache.  Depending on the specific computer described, each processing element is generally ]]
[[image:Misd Arch Solihin2.jpg|thumb|center|400px|alt=MISD computer architecture outline.|From NCSU CSC/ECE 506 Spring 2012 Lecture 1 notes[[#References|<sup>[5]</sup>]].]]


From the image, we see that the data stream has one clear entrance and exit into the system.  Each processing element has access to a collective and/or individual instruction cache.  Depending on the specific system described, each processing element is generally function specific or predestined; but in some systems (similar to [http://en.wikipedia.org/wiki/IWarp iWarp]), each processing element may be quite advanced.
From the image, we see that the data stream has one clear entrance and exit into the system.  Each processing element has access to a collective and/or individual instruction cache.  Depending on the specific system described, each processing element is generally function specific or predestined; but in some systems (similar to [http://en.wikipedia.org/wiki/IWarp iWarp]), each processing element may be quite advanced.

Revision as of 21:41, 26 January 2012

MISD

Micheal J. Flynn introduced the idea of an MISD (Multiple Instruction, Single Data) computer architectures in his original taxonomy in 1966.[1]

Dr. Yan Solihin defines MISD as "..an architecture in which multiple processing elements execute from different instruction streams, and data is passed from one processing element to the next."[2] He also notes that MISD architectures are restricted to certain types of computations due to the requirement of data-passing between processing elements.[2] Each processing element executes different instructions on the data stream.[3] Every time the data is processed by a processing element, we can always argu that the data is no longer the original data introduced at the start of the stream.[4]

MISD computer architecture outline.
From NCSU CSC/ECE 506 Spring 2012 Lecture 1 notes[5].

From the image, we see that the data stream has one clear entrance and exit into the system. Each processing element has access to a collective and/or individual instruction cache. Depending on the specific system described, each processing element is generally function specific or predestined; but in some systems (similar to iWarp), each processing element may be quite advanced.

MISD Computers

It is widely believed that no actual MISD computer exists in practice. Some arguments exist that pipelined vector processors


References

  1. Flynn, M. (1972). "Some Computer Organizations and Their Effectiveness". IEEE Trans. Comput. C-21: 948.
  2. Solihin, Y. (2008). "Fundamentals of Parallel Computer Architecture: Multichip and Multicore Systems". Solihin Publishing & Consulting LLC. C-1: 12.
  3. CSC 8383 Lecuture 5
  4. MISD wiki
  5. ECE506 Spring 2012 Lecture 1
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