CSC/ECE 506 Spring 2011/ch11 BB EP: Difference between revisions

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== Race Conditions ==
== Race Conditions ==
In a distributed shared memory system with caching, the emergence of race conditions is extremely likely.  This is mainly due to the lack of a bus for serialization of actions.  It is further compounded by the problem of network errors and congestion.
The early invalidation case from Section 11.4 in Solihin is an excellent example of a race condition that can arise in a distributed system.  Recall the diagram from the text, and the cache coherence actions.
1. A sends a read request to home.
2. Home replies with data (but the message gets delayed).
3. B sends a write request to home.
4. Home sends invalidation to A, and it arrives before the ReplyD
=== Prevention in the SCI Protocol ===
Race conditions are almost non-existent in the SCI protocol, due primarily to the protocol's design.
==== Head Node ====
==== Memory Access ====
==== Atomic Transactions ====
=== Possible Race Conditions ===
==== Communication Delays ====
==== Concurrent List Deletions ====
==== Simultaneous Deletion and Invalidation ====


== Summary ==
== Summary ==

Revision as of 01:35, 18 April 2011

History

Background

State Diagrams

Memory

Processors

Race Conditions

In a distributed shared memory system with caching, the emergence of race conditions is extremely likely. This is mainly due to the lack of a bus for serialization of actions. It is further compounded by the problem of network errors and congestion.

The early invalidation case from Section 11.4 in Solihin is an excellent example of a race condition that can arise in a distributed system. Recall the diagram from the text, and the cache coherence actions.

1. A sends a read request to home. 2. Home replies with data (but the message gets delayed). 3. B sends a write request to home. 4. Home sends invalidation to A, and it arrives before the ReplyD


Prevention in the SCI Protocol

Race conditions are almost non-existent in the SCI protocol, due primarily to the protocol's design.

Head Node

Memory Access

Atomic Transactions

Possible Race Conditions

Communication Delays

Concurrent List Deletions

Simultaneous Deletion and Invalidation

Summary

Definitions and Terms

References