CSC/ECE 506 Fall 2007/wiki2 05 sa: Difference between revisions
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| 2 | | 2 | ||
| 64 bytes (for both L1 & L2) | | 64 bytes (for both L1 & L2) | ||
| L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 512KB to | | L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 512KB to 1MB per core | ||
| L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative | | L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative | ||
| Modified Owner Exclusive Shared Invalid (MOESI) | | Modified Owner Exclusive Shared Invalid (MOESI) | ||
| Line 30: | Line 30: | ||
| 2 | | 2 | ||
| 64 bytes (for both L1 & L2) | | 64 bytes (for both L1 & L2) | ||
| L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - | | L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 1MB per core | ||
| L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative | | L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative | ||
| Modified Owner Exclusive Shared Invalid (MOESI) | | Modified Owner Exclusive Shared Invalid (MOESI) | ||
| Line 37: | Line 37: | ||
| 2 | | 2 | ||
| 64 bytes (for both L1 & L2) | | 64 bytes (for both L1 & L2) | ||
| L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - | | L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 1MB per core | ||
| L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative | | L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative | ||
| Modified Owner Exclusive Shared Invalid (MOESI) | | Modified Owner Exclusive Shared Invalid (MOESI) | ||
|- | |- | ||
| Pentium D | |||
| 2 | |||
| L1 - 64 byte lines<br/>L2 - 128 byte lines | |||
| L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)<br/>L2 - 1MB or 2MB per core | |||
| L1 - 4 way<br/>L2 - 8 way | |||
|- | |||
! colspan="6" style="background:#ffdead;" | Singlecore Processors | ! colspan="6" style="background:#ffdead;" | Singlecore Processors | ||
|- | |- | ||
Revision as of 18:01, 24 September 2007
Cache sizes in multicore architectures
Topic - Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.
| Multicore Processors | |||||
|---|---|---|---|---|---|
| Processor Name | Number of Levels | Line Size | Cache Size | Associativity | Coherence Protocol |
| AMD Athlon 64 X2 | 2 | 64 bytes (for both L1 & L2) | L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 512KB to 1MB per core |
L1 - 2 way (Data and Instruction cache) L2 - 16 way associative |
Modified Owner Exclusive Shared Invalid (MOESI) |
| AMD Athlon 64 FX | 2 | 64 bytes (for both L1 & L2) | L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core |
L1 - 2 way (Data and Instruction cache) L2 - 16 way associative |
Modified Owner Exclusive Shared Invalid (MOESI) |
| AMD Athlon Opteron (marketed for servers) |
2 | 64 bytes (for both L1 & L2) | L1 - 64KB (Data) + 64KB (Instruction) per core L2 - 1MB per core |
L1 - 2 way (Data and Instruction cache) L2 - 16 way associative |
Modified Owner Exclusive Shared Invalid (MOESI) |
| Pentium D | 2 | L1 - 64 byte lines L2 - 128 byte lines |
L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used) L2 - 1MB or 2MB per core |
L1 - 4 way L2 - 8 way | |
| Singlecore Processors | |||||
| Bottom | |||||