CSC/ECE 506 Fall 2007/wiki2 05 sa: Difference between revisions

From Expertiza_Wiki
Jump to navigation Jump to search
No edit summary
No edit summary
Line 11: Line 11:
|+'''Detail of Caches'''
|+'''Detail of Caches'''
|-
|-
! colspan="5" style="background:#ffdead;" | Multicore Processors
! colspan="6" style="background:#ffdead;" | Multicore Processors
|-
|-
! Processor Name
! Processor Name
Line 17: Line 17:
! Line Size
! Line Size
! Size
! Size
! Associativity
! Coherence Protocol
! Coherence Protocol
|-
|-
| AMD Athlon 64 FX
| 2
| 64 bytes (for both L1 & L2)
| L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - up to 1 MB per core
| L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
| Modified Owner Exclusive Shared Invalid (MOESI)
|-
|-
! colspan="5" style="background:#ffdead;" | Singlecore Processors
|
! colspan="6" style="background:#ffdead;" | Singlecore Processors
|-
|-
| colspan="5" style="border-bottom:3px solid grey;" align="center" | Bottom
| colspan="6" style="border-bottom:3px solid grey;" align="center" | Bottom
|-
|-
|}
|}

Revision as of 17:31, 24 September 2007

Cache sizes in multicore architectures

Topic - Create a table of caches used in current multicore architectures, including such parameters as number of levels, line size, size and associativity of each level, latency of each level, whether each level is shared, and coherence protocol used. Compare this with two or three recent single-core designs.


Detail of Caches
Multicore Processors
Processor Name Number of Levels Line Size Size Associativity Coherence Protocol
AMD Athlon 64 FX 2 64 bytes (for both L1 & L2) L1 - 64KB (Data) + 64KB (Instruction) per core
L2 - up to 1 MB per core 		L1 - 2 way (Data and Instruction cache)
L2 - 16 way associative 		Modified Owner Exclusive Shared Invalid (MOESI)
Singlecore Processors
Bottom
Retrieved from "https://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Fall_2007/wiki2_05_sa&oldid=4364"