CSC/ECE 506 Fall 2007/wiki2 7 ss: Difference between revisions
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[1] A Formal Specification of Intel® Itanium® Processor Family Memory Ordering: http://www.intel.com/design/itanium/downloads/251429.htm | [1] A Formal Specification of Intel® Itanium® Processor Family Memory Ordering: http://www.intel.com/design/itanium/downloads/251429.htm | ||
[2] | [2] HP: http://h18000.www1.hp.com/alphaserver/download/architecture.pdf?jumpid=reg_R1002_USEN | ||
[3] SGI: http://www.sgi.com/pdfs/3935.pdf | |||
Revision as of 09:35, 22 September 2007
Cache-to-Cache Sharing
Cache-to-cache sharing is a technique to supply the block for a BusRd(Bus Read) transaction from cache instead of main memory. Stanford DASH multiprocessor used cache-to-cache transfers.
Advantages
Multiprocessors with physically distributed memory because the latency to obtain data from a nearby cache may be much smaller than that for a faraway memory unit.
Disadvantages
Cache-to-cache sharing adds complexity to bus-based protocol in that main memory must wait until it is certain that no cache will supply the data before driving the bus and also if the data resides in multiple caches, a selection algorithm is needed to determine which one will provide the data.
References
[1] A Formal Specification of Intel® Itanium® Processor Family Memory Ordering: http://www.intel.com/design/itanium/downloads/251429.htm
[2] HP: http://h18000.www1.hp.com/alphaserver/download/architecture.pdf?jumpid=reg_R1002_USEN
[3] SGI: http://www.sgi.com/pdfs/3935.pdf