CSC/ECE 506 Spring 2010/chapter 10: Difference between revisions
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== Introduction == | == '''Introduction''' == | ||
This material gives a brief explanation about the intuition behind using relaxed memory consistency models that we have studied in class. It also explains about the consistency models in real multiprocessor systems like Digital Alpha, Sparc V9 RMO, IBM Power PC, Intel Pentium, and processors from Sun Microsystems. A brief about the limitations of cache-coherent directory-based systems is also provided. | This material gives a brief explanation about the intuition behind using relaxed memory consistency models that we have studied in class. It also explains about the consistency models in real multiprocessor systems like Digital Alpha, Sparc V9 RMO, IBM Power PC, Intel Pentium, and processors from Sun Microsystems. A brief about the limitations of cache-coherent directory-based systems is also provided. | ||
== '''Memory Consistency Models''' == | |||
Revision as of 02:02, 13 April 2010
Introduction
This material gives a brief explanation about the intuition behind using relaxed memory consistency models that we have studied in class. It also explains about the consistency models in real multiprocessor systems like Digital Alpha, Sparc V9 RMO, IBM Power PC, Intel Pentium, and processors from Sun Microsystems. A brief about the limitations of cache-coherent directory-based systems is also provided.