Chp8 my: Difference between revisions

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====AMD====
====AMD====


===MOESI protocol===
===MOESI protocol (AMD)===


====Intel====
===AMD====
 
====AMD====


AMD  Opteron is using MOESI (modified, owned, exclusive, shared, invalid) protocol for cache sharing. In addition to the four states in MESI, which is adopted by Intel for their Xeon processors, a fifth state "Owned" appears here representing data that is both modified and shared. Using MOESI, writing modified data back to main memory is avoided before being shared, which could save bandwidth and gain much faster access to users to the cache.
AMD  Opteron is using MOESI (modified, owned, exclusive, shared, invalid) protocol for cache sharing. In addition to the four states in MESI, which is adopted by Intel for their Xeon processors, a fifth state "Owned" appears here representing data that is both modified and shared. Using MOESI, writing modified data back to main memory is avoided before being shared, which could save bandwidth and gain much faster access to users to the cache.

Revision as of 01:30, 26 March 2010

In computing, cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.

Cache Coherence

Definition

Coherency protocol

MSI protocol

Intel

AMD

MESI protocol

In MESI protocol, there are four cache block status:

  • 1. Modified (M): the cache block valid in only one cache and the value is like different from the main memory.
  • 2. Exclusive (E): the cache block is valid and clean, but only resides in one cache.
  • 3. Shared (S): the cache block is valid and clean, but may exist in multiple caches.
  • 4. Invalid (I): the cache block is invalid.


This figure shows the status change when bus traction generated.

Intel

AMD

MOESI protocol (AMD)

====AMD====

AMD Opteron is using MOESI (modified, owned, exclusive, shared, invalid) protocol for cache sharing. In addition to the four states in MESI, which is adopted by Intel for their Xeon processors, a fifth state "Owned" appears here representing data that is both modified and shared. Using MOESI, writing modified data back to main memory is avoided before being shared, which could save bandwidth and gain much faster access to users to the cache.

The states of the MOESI protocol are:

  • Invalid—A cache line in the invalid state does not hold a valid copy of the data. Valid copies of the data can be either in main memory or another processor cache.
  • Exclusive—A cache line in the exclusive state holds the most recent, correct copy of the data. The copy in main memory is also the most recent, correct copy of the data. No other processor holds a copy of the data.
  • Shared—A cache line in the shared state holds the most recent, correct copy of the data. Other processors in the system may hold copies of the data in the shared state, as well. If no other processor holds it in the owned state, then the copy in main memory is also the most recent.
  • Modified—A cache line in the modified state holds the most recent, correct copy of the data. The copy in main memory is stale (incorrect), and no other processor holds a copy.
  • Owned—A cache line in the owned state holds the most recent, correct copy of the data. The owned state is similar to the shared state in that other processors can hold a copy of the most recent, correct data. Unlike the shared state, however, the copy in main memory can be stale (incorrect). Only one processor can hold the data in the owned state—all other processors must hold the data in the shared state.


The figure below shows the five different states of MOESI protocol.

Dragon protocol

Intel

AMD

References

  1. Cache Coherence
  2. Cache consistency & MESI Intel
  3. A closer look at AMD's dual-core architecture
  4. CSE 400 – Related Work: Instructions & Example
  5. Trace-Driven Simulation of the MSI, MESI and Dragon Cache Coherence Protocols
  6. Understanding the Detailed Architecture of AMD's 64 bit Core
  7. MSI,MESI,MOESI sheet
  8. AMD64 Architecture Programmer’s Manual