CSC/ECE 506 Fall 2007/wiki1 4 JHSL

Architectual Trends

General trends

During the last ten years general direction of the architectural trends did not change much: the logic density is still increasing, number of CPUs per machine is rising, memory size and bandwidth are growing. The only difference is that the most of the yesterday's bleeding-edge technologies have made its way to consumer market and now available for individual users, not just big companies and research centers. Ready availability of such technologies, in turn, has fed the hi-end portion of the market and most of the commodity parts are preferred choice for the state-of-the art computer building. While general direction is still the same, it is important to note some of the technological advances that can potentially set new direction for the next generation of the computers. Further in this article bottom-up approach will be used to discuss architectural trends: first the major advancements in the underlaying technology will be mentioned, and later, discussion of the higher-level architecture will follow.

"Rock bottom" (Silicone/Carbon)

Trend of a transistor size, current production specs and future plans.

The very basic building block of electronic technology, the transistor, has shrank dramatically during the past decade. Processors built on 45nm technology are widly available on the market. According to Intel's press release from the beginning of this year, "Just a decade ago, the state-of-the-art process technology was 250nm, meaning transistor dimensions were approximately 5.5 times the size and 30 times the area of the technology announced today by Intel" [1]. Here, on the image below you can see a 45nm 6-transistor SRAM cell, developed by Intel [2].
http://www.intel.com/pressroom/images/manufacturing/45nm_SRAM_Cell_sm.jpg
It is worth mentioning, that while 45nm is current production specification, all major players have already announced plans to decrease trace width even further.

Wafer size and CPU footprint

While the transistor size continues to decrease, the manufacturers have been consistently moving towards larger silicone wafer sizes. Today most of the CPUs are produces on 300mm wafers. Combined with increased logic density, this allows to produce more processors from a single wafer, therefore significantly decreasing overall production costs.
http://www.intel.com/pressroom/images/manufacturing/45nm_wafer_photo_2_sm.JPG
Image: Intel engineer holds 300 mm wafer.

The Future is here: Carbon nanotubes

While silicone is still the primary choice for today's technology, new material has attracted attention of the semiconductor industry: carbon nanotubes. Microscopic cyllinders of only about 1nm in diameter (hence the name), possess very interesting electrical properties: under some conditions they can be metallic, and under other - semiconductors. In 2001 IBM was successful in constructing first carbon-based transistors [3].

Longer, Wider, Deeper and Smarter:

Wider internal buses, more logical units

• (AMD K8, Intel Core 2, SSE1/2/3/4)

Deeper caches

• (L3 caches, smart prefetch and so on)

"Smarter" CPUs

• Itanium
  • (explicit parallelism)
• AMD Opteron
  • (built-in memory controller and bus logic)
• Intel P4
  • (complex branch prediction)

"My dual quad-core with quad-SLI"

Sun Niagara

• 4 threads per core
• 4 cores per CPU,
• multiple CPUs per box

"Personal Petaflop": The Latest in GPU world

• ATI Radeon
• NVidia GeForce

Buses and memory

Parallel Buses

The PCI (Peripheral Component Interconnect) architecture was introduced by Intel in 1992, but did not gain significant traction over the established VESA Local Bus (VLB) in the consumer market until 1994. It was originally released only as a component specification, but later revisions added requirements for shape of connectors and motherboard slots. The bus supports both 32-bit and 4-bit bus widths. Four interrupt lines are shared by all devices on the bus, but are shifted by one position between devices so they are used evenly. For example, interrupt "A" on the first device is shifted to interrupt "B" on the second device, to interrupt "C" on the third device, and so on. The original specification provided a 33 MHz bus speed for a peak transfer rate of 133 MB/second for a 32-bit bus, and 266 MB/second for a 64-bit bus. Later revisions of the standard increased the frequency to 66 MHz, with a peak transfer rate of 533 MB/second for a 64-bit bus.

• Past:
  • PCI
  • PCI-X
  • AGP

Serial Buses

• Future:
  • PCI-E
  • AMD HyperTransport
  • Intel EV?

Memory

• [G]DDR2/3/4
• FB-DIMM

References / Extra info

1. http://www.intel.com/pressroom/archive/releases/20070128comp.htm
2. http://www.intel.com/pressroom/archive/releases/20060125comp.htm
3. http://domino.research.ibm.com/comm/pr.nsf/pages/news.20010425_Carbon_Nanotubes.html

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Intel P6 Arch http://studies.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium2%20(mpr).pdf
Intel Netburst http://en.wikipedia.org/wiki/NetBurst
Intel P4 microarch http://www.intel.com/technology/itj/q12001/pdf/art_2.pdf
Peripheral Component Interconnect (PCI) http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect AMD K7 http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22054.pdf
AMD K8 http://www.cpuid.com/reviews/K8/index.php
Intel Itanium http://en.wikipedia.org/wiki/Image:Itanium_arch.png