CSC/ECE 506 Fall 2007/wiki1 4 JHSL: Difference between revisions

From Expertiza_Wiki
Jump to navigation Jump to search
Line 50: Line 50:
* [G]DDR2/3/4
* [G]DDR2/3/4
* FB-DIMM
* FB-DIMM
= References / Extra info =

Revision as of 12:48, 4 September 2007

Industry Trends

"Rock bottom" (Silicone/Carbon)

Trend of a transistor size, current production specs and future plans.

Platter size, silicone real estate and CPU footprint

"The silicone is dead. Again." (the latest breakthroughs in silicone transistor size/speed)

The Future is here: Carbon nanotubes

Longer, Wider, Deeper and Smarter:

Longer pipelines (Intel Netburst)

Wider internal buses, more logical units

  • (AMD K8, Intel Core 2, SSE1/2/3/4)

Deeper caches

  • (L3 caches, smart prefetch and so on)

"Smarter" CPUs

  • Itanium
    • (explicit parallelism)
  • AMD Opteron
    • (built-in memory controller and bus logic)
  • Intel P4
    • (complex branch prediction)

"My dual quad-core with quad-SLI"

Intel Hyperthreading and Core 2 Duo/Quad

AMD X2, Quadcore

Sun Niagara

  • 4 threads per core
  • 4 cores per CPU,
  • multiple CPUs per box

IBM Cell

"Personal Petaflop": The Latest in GPU world

  • ATI Radeon
  • NVidia GeForce

Buses and memory

Parallel Buses

  • Past:
    • PCI
    • PCI-X
    • AGP

Serial Buses

  • Future:
    • PCI-E
    • AMD HyperTransport
    • Intel EV?

Memory

  • [G]DDR2/3/4
  • FB-DIMM

References / Extra info

Retrieved from "https://wiki.expertiza.ncsu.edu/index.php?title=CSC/ECE_506_Fall_2007/wiki1_4_JHSL&oldid=2296"