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| =<center>Cache sizes in multicore architectures</center>=
| | This page was mistakenly created. Please access this page at - http://pg.ece.ncsu.edu/mediawiki/index.php/CSC/ECE_506_Fall_2007/wiki2_5_as |
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| ''Topic'' - Create a table of caches used in current multicore architectures,
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| including such parameters as number of levels, line size, size and
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| associativity of each level, latency of each level, whether each level
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| is shared, and coherence protocol used. Compare this with two or three
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| recent single-core designs.
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| {| border="1" cellpadding="5" cellspacing="0" align="center"
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| |+'''Detail of Caches'''
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| |-
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| ! colspan="6" style="background:#ffdead;" | Multicore Processors
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| |-
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| ! Processor Name
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| ! Number of Levels
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| ! Line Size
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| ! Cache Size
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| ! Associativity
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| ! Coherence Protocol
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| |-
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| | AMD Athlon 64 X2
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| | 2
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| | 64 bytes (for both L1 & L2)
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| | L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 512KB to 1MB per core
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| | L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
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| | Modified Owner Exclusive Shared Invalid (MOESI)
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| |-
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| | AMD Athlon 64 FX
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| | 2
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| | 64 bytes (for both L1 & L2)
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| | L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 1MB per core
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| | L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
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| | Modified Owner Exclusive Shared Invalid (MOESI)
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| |-
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| | AMD Athlon Opteron<br/>(marketed for servers)
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| | 2
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| | 64 bytes (for both L1 & L2)
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| | L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - 1MB per core
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| | L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
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| | Modified Owner Exclusive Shared Invalid (MOESI)
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| |-
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| | Intel Pentium D
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| | 2
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| | L1 - 64 byte lines<br/>L2 - 128 byte lines
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| | L1 - 16 KB (data only. Instead of instruction cache, a "150KB trace cache" is used)<br/>L2 - 1MB or 2MB per core
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| | L1 - 4 way<br/>L2 - 8 way
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| | Modified Exclusive Shared Invalid (MESI)
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| |-
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| | Intel Pentium Dual Core
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| | 2
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| | L1 - 64 byte lines<br/>L2 - 64 byte lines
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| | L1 - 32 KB (both Data and Instruction cache)<br/>L2 - 1MB or 2MB per core
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| | L1 - 4 way<br/>L2 - 8 way
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| | Modified Exclusive Shared Invalid (MESI)
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| |-
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| | Intel Core 2 Duo
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| | 2
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| | L1 - 64 byte lines<br/>L2 - 64 byte lines
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| | L1 - 32 KB (each for Data and Instruction cache)<br/>L2 - 2MB or 4MB
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| | L1 - 4 way<br/>L2 - 8 way
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| | Modified Exclusive Shared Invalid (MESI)
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| |-
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| | Broadcom SiByte SB1250
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| | 2
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| | L1 - 32 byte lines<br/>L2 - 32 byte lines
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| | L1 - 32 KB (a piece for Data and Instruction caches)<br/>L2 - 512KB
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| | L1 - 2 way<br/>L2 - 4 way
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| | Modified Exclusive Shared Invalid (MESI)
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| |-
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| | Sun Microsystems UltraSPARC IV
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| | 2
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| | L1 - 128byte lines<br/>L2 - 128 byte lines
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| | L1 - 64KB data, 32KB instruction<br/>L2 - up to 16MB
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| | L2 - 2 way
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| | Modified Owner Exclusive Shared Invalid (MOESI)
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| |-
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| | IBM Cell Processor
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| | 2
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| | Not Available
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| | L1 - 32 KB (a piece for both data and instruction caches)<br/>L2 - 512KB
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| | L1 - 2 way instruction, 4 way data<br/>L2 - 8 way
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| | Modified Exclusive Shared Invalid (MESI)
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| |-
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| ! colspan="6" style="background:#ffdead;" | Singlecore Processors
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| |-
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| | AMD Athlon 64
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| | 2
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| | L1 - 64 byte lines<br/>L2 - 64 byte lines
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| | L1 - 64 KB (each for Data and Instruction cache)<br/>L2 - 512KB
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| | L1 - 2 way<br/>L2 - 16 way
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| | Modified Owner Exclusive Shared Invalid (MOESI)
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| |-
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| | AMD K6 / K6 III
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| | 2
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| | L1 - 32 byte lines<br/2>L2 -
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| | L1 - 32KB data (2-way associative), 32KB instruction (2-Way associative)<br/>L2 - 256KB
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| | L1 - 2 way<br/>L2 - 4 way
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| | Modified Exclusive Shared Invalid (MESI)
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| |-
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| | Intel Pentium 4
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| | 2
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| | L1 - 64 byte lines<br/>L2 - 128 byte lines
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| | L1 - 8 KB (data only. Instead of instruction cache, a "150KB trace cache" is used))<br/>L2 -256KB, 512KB or 1MB
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| | L1 - 4 way<br/>L2 - 8 way
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| | Modified Exclusive Shared Invalid (MESI)
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| |-
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| | Intel PentiumIII 600
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| | 2
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| | L1 - <br/>L2 -
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| | L1 - 16 KB data, 16K Instruction<br/>L2 - 256KB
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| | L1 - <br/>L2 - 8 way
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| |-
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| | Intel Core Solo
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| | 2
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| | L1 - <br/>L2 -
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| | L1 - 32 KB data, 32KB Instruction<br/>L2 - 2MB
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| | L1 - <br/>L2 -
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| |}
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| == Conclusion ==
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| == References ==
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| [1] http://www.amd.com/us-en/Processors/ProductInformation
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| [2] http://www.broadcom.com/products/Enterprise-Networking/Communications-Processors/BCM1250
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| [3] http://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_970MP_Microprocessor
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| [4] http://www.intel.com/products/processor/xeon7000/documentation.htm?iid=products_xeon7000+tab_techdocs#datasheets
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| [5] http://www.sun.com/processors/UltraSPARC-IV/
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| [6] http://www.sun.com/processors/UltraSPARC-IV+/
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| [7] http://www.sun.com/processors/UltraSPARC-T1/
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| [8] http://www.streamprocessors.com/streamprocessors/Home/Products/Storm-1Family.html
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| [9] http://www.netlib.org/utk/papers/advanced-computers/pa-risc.html
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| [10] http://www.netlib.org/utk/papers/advanced-computers/power4.html
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| [11] http://www.netlib.org/utk/papers/advanced-computers/power5.html
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| [12] http://en.wikipedia.org/wiki/Cell_microprocessor
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| [13] http://techreport.com/articles.x/8236/2
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| [14] http://www.hardwaresecrets.com/article/481/9
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