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| =<center>Cache sizes in multicore architectures</center>=
| | This page was mistakenly created. Please access this page at - http://pg.ece.ncsu.edu/mediawiki/index.php/CSC/ECE_506_Fall_2007/wiki2_5_as |
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| Topic - Create a table of caches used in current multicore architectures,
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| including such parameters as number of levels, line size, size and
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| associativity of each level, latency of each level, whether each level
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| is shared, and coherence protocol used. Compare this with two or three
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| recent single-core designs.
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| {| border="1" cellpadding="5" cellspacing="0" align="center"
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| |+'''Detail of Caches'''
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| |-
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| ! colspan="6" style="background:#ffdead;" | Multicore Processors
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| |-
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| ! Processor Name
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| ! Number of Levels
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| ! Line Size
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| ! Size
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| ! Associativity
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| ! Coherence Protocol
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| |-
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| | AMD Athlon 64 FX
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| | 2
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| | 64 bytes (for both L1 & L2)
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| | L1 - 64KB (Data) + 64KB (Instruction) per core<br/>L2 - up to 1 MB per core
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| | L1 - 2 way (Data and Instruction cache)<br/>L2 - 16 way associative
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| | Modified Owner Exclusive Shared Invalid (MOESI)
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| |-
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| ! colspan="6" style="background:#ffdead;" | Singlecore Processors
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| |-
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| | colspan="6" style="border-bottom:3px solid grey;" align="center" | Bottom
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| |-
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| |}
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Latest revision as of 01:51, 25 September 2007